Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
3.8.2.10 CAM_PRM Registers
3.8.2.10.1 CAM_PRM Registers
Table 3-403. CAM_PRM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
RM_RSTST_CAM RW 32 0x0000 0058 0x4830 6F58 C
PM_WKDEP_CAM RW 32 0x0000 00C8 0x4830 6FC8 W
PM_PWSTCTRL_CAM RW 32 0x0000 00E0 0x4830 6FE0 W
PM_PWSTST_CAM R 32 0x0000 00E4 0x4830 6FE4 C
PM_PREPWSTST_CAM RW 32 0x0000 00E8 0x4830 6FE8 C
3.8.2.10.2 CAM_PRM Registers
Table 3-404. RM_RSTST_CAM
Address Offset 0x0000 0058
Physical Address 0x4830 6F58 Instance CAM_PRM
Description This register logs the different reset sources of the CAMERA domain. Each bit is set upon release of the
domain reset signal. Must be cleared by software.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
GLOBALCOLD_RST
DOMAINWKUP_RST
GLOBALWARM_RST
COREDOMAINWKUP_RST
Bits Field Name Description Type Reset
31:4 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000000
3 COREDOMAINWKUP_RST CORE domain wake-up reset RW 0x0
Read 0x0: No power domain wake-up reset.
Write 0x0: Status bit unchanged
Read 0x1: CAM domain has been reset following a
CORE power domain wake-up from OFF to ON.
Write 0x1: Status bit is cleared to 0.
2 DOMAINWKUP_RST Power domain wake-up reset RW 0x0
Read 0x0: No power domain wake-up reset.
Write 0x0: Status bit unchanged
Read 0x1: CAM domain has been reset following a
CAMERA power domain wake-up.
Write 0x1: Status bit is cleared to 0.
607 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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