Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
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Table 3-340. CORE_PRM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
RM_RSTST_CORE RW 32 0x0000 0058 0x4830 6A58 C
PM_WKEN1_CORE RW 32 0x0000 00A0 0x4830 6AA0 W
PM_MPUGRPSEL1_CORE RW 32 0x0000 00A4 0x4830 6AA4 W
PM_IVA2GRPSEL1_CORE RW 32 0x0000 00A8 0x4830 6AA8 W
PM_WKST1_CORE RW 32 0x0000 00B0 0x4830 6AB0 C
PM_WKST3_CORE RW 32 0x0000 00B8 0x4830 6AB8 C
PM_PWSTCTRL_CORE RW 32 0x0000 00E0 0x4830 6AE0 W
PM_PWSTST_CORE R 32 0x0000 00E4 0x4830 6AE4 C
PM_PREPWSTST_CORE RW 32 0x0000 00E8 0x4830 6AE8 C
PM_WKEN3_CORE RW 32 0x0000 00F0 0x4830 6AF0 W
PM_IVA2GRPSEL3_CORE RW 32 0x0000 00F4 0x4830 6AF4 W
PM_MPUGRPSEL3_CORE RW 32 0x0000 00F8 0x4830 6AF8 W
3.8.2.5.2 CORE_PRM Registers
Table 3-341. RM_RSTST_CORE
Address Offset 0x0000 0058
Physical Address 0x4830 6A58 Instance CORE_PRM
Description This register logs the different reset sources of the CORE domain. Each bit is set upon release of the
domain reset signal. Must be cleared by software.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
GLOBALCOLD_RST
DOMAINWKUP_RST
GLOBALWARM_RST
Bits Field Name Description Type Reset
31:3 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
2 DOMAINWKUP_RST Power domain wake-up reset RW 0x0
Read 0x0: No power domain wake-up reset.
Write 0x0: Status bit unchanged
Read 0x1: CORE domain has been reset following a
CORE power domain wake-up.
Write 0x1: Status bit is cleared to 0.
1 GLOBALWARM_RST Global warm reset RW 0x0
Read 0x0: No global warm reset.
Write 0x0: Status bit unchanged
Read 0x1: CORE domain has been reset upon a global
warm reset
Write 0x1: Status bit is cleared to 0.
576 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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