Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 583 / 3738

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PRCM Register Manual
Bits Field Name Description Type Reset
4 GRPSEL_HSOTGUSB Select the HS OTG USB in the IVA2 wake-up events RW 0x1
group
0x0: HS OTG USB is not attached to the IVA2 wake-up
events group.
0x1: HS OTG USB is attached to the IVA2 wake-up
events group.
3:0 RESERVED Write 0x8 for future compatibility. Read returns 0x8. R 0x8
Table 3-348. Register Call Summary for Register PM_IVA2GRPSEL1_CORE
PRCM Functional Description
• Device Wake-Up Events : [0]
PRCM Basic Programming Model
• PM_ <processor_name> GRPSEL_ <domain_name> (Processor Group Selection Register) : [1]
PRCM Register Manual
• CORE_PRM Register Summary : [2]
Table 3-349. PM_WKST1_CORE
Address Offset 0x0000 00B0
Physical Address 0x4830 6AB0 Instance CORE_PRM
Description This register logs module wake-up events. Must be cleared by software. If it is not cleared, it prevents
further domain transition.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED
ST_I2C3 ST_I2C2 ST_I2C1
ST_MMC3 ST_MMC2 ST_MMC1
ST_GPT11 ST_GPT10
ST_UART2 ST_UART1
RESERVED RESERVED ST_MCSPI4 ST_MCSPI3 ST_MCSPI2 ST_MCSPI1
ST_MCBSP5 ST_MCBSP1
ST_HSOTGUSB
Bits Field Name Description Type Reset
31 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0
30 ST_MMC3 MMC 3 Wake-up status RW 0x0
Read 0x0: MMC 3 wake-up did not occur or was masked.
Write 0x0: Status bit unchanged
Read 0x1: MMC 3 wake-up occurred.
Write 0x1: Status bit is cleared to 0.
29:26 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0
25 ST_MMC2 MMC 2 Wake-up status RW 0x0
Read 0x0: MMC 2 wake-up did not occur or was masked.
Write 0x0: Status bit unchanged
Read 0x1: MMC 2 wake-up occurred.
Write 0x1: Status bit is cleared to 0.
24 ST_MMC1 MMC 1 Wake-up status RW 0x0
Read 0x0: MMC 1 wake-up did not occur or was masked.
Write 0x0: Status bit unchanged
Read 0x1: MMC 1 wake-up occurred.
Write 0x1: Status bit is cleared to 0.
23:22 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0
583 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated