Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
3.8.2.2.2 IVA2_PRM Registers
Table 3-298. RM_RSTCTRL_IVA2
Address Offset 0x0000 0050
Physical Address 0x4830 6050 Instance IVA2_PRM
Description This register controls the release of the IVA2 sub-system resets.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RST3_IVA2 RST2_IVA2 RST1_IVA2
Bits Field Name Description Type Reset
31:3 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
2 RST3_IVA2 Video sequencer reset control RW 0x1
0x0: Video sequencer reset is cleared
0x1: Resets video sequencer
1 RST2_IVA2 IVA2 - MMU reset control and Video Sequencer RW 0x1
hardware accelerator reset control
0x0: IVA2 - MMU reset and Video Sequencer hardware
accelerator reset are cleared
0x1: Resets IVA2 - MMU and Video Sequencer hardware
accelerator
0 RST1_IVA2 IVA2 - DSP reset control RW 0x1
0x0: IVA2 - DSP reset is cleared
0x1: Resets IVA2 - DSP
Table 3-299. Register Call Summary for Register RM_RSTCTRL_IVA2
PRCM Functional Description
• Local Reset Sources : [0] [1] [2]
• IVA2.2 Subsystem Power-Up Sequence : [3] [4] [5]
• IVA2 Software Reset Sequence : [6] [7] [8]
• IVA2 Global Warm Reset Sequence : [9]
• IVA2 Power Domain Wake-Up Cold Reset Sequence : [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
PRCM Basic Programming Model
• RM_RSTCTRL_ <domain_name> (Reset Control Register) : [20]
PRCM Register Manual
• IVA2_PRM Register Summary : [21]
549 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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