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PRCM Functional Description
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•
All the power domain warm resets are asserted.
•
DPLL1 and DPLL3 transit to bypass mode. DPLL2, DPLL4, and DPLL5 transit to stop mode. The
system clock, SYS_CLK, continues running at system clock frequency.
•
The registers sensitive to a warm reset are synchronously reset (PRM and CM register sets).
•
The CM cuts all the clocks not requested, according to the register reset value settings.
2. The global warm reset is released and extended after release of the warm reset source until the
following conditions are met:
•
Device reset manager counter overflows (set up by the PRCM.
[7:0] RSTTIME1 bit
field).
•
Voltage domains (VDD1, VDD2, VDD4 and VDD5) are stable.
NOTE:
Voltage stabilization is an additional condition if voltage scaling was performed before
the assertion of the warm reset.
3. The CORE domain is released from reset (warm sensitive modules in CORE power domain).
4. The MPU_CLK clock is running.
5. The MPU power domain is released from reset. The MPU boots.
NOTE:
•
The IVA2 power domain is held under reset after global warm reset by assertion of the
software source of the reset.
•
Power domains such as PER, DSS, CAM, SGX, and NEON are held under reset after
global warm reset until the MPU software enables their interface clock.
3.5.1.9.3 IVA2.2 Subsystem Power-Up Sequence
This section describes the power-up reset sequence and timing relationships of the IVA2.2 subsystem.
The assumptions are:
•
The MPU is running.
•
All sources of reset to the IVA2.2 subsystem are released except for the software sources of reset.
shows the IVA2.2 power-up sequence.
272
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated