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PRCM Register Manual
Bits
Field Name
Description
Type
Reset
31:3
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x00000000
2
RST_DPLL3
DPLL3 software reset control. This bit is reset only upon
RW
0x0
a global cold source of reset.
0x0: DPLL3 software reset is cleared.
0x1: Asserts the DPLL3 software reset and induces a
global cold reset on the whole chip. The software must
ensure the SDRAM is properly put in sef-refresh mode
before applying this reset.
1
RST_GS
Global software reset control. This bit is reset upon any
RW
0x0
global source of reset (warm and cold).
0x0: Global software reset is cleared.
0x1: Asserts a global software reset.
0
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x0
Table 3-456. Register Call Summary for Register PRM_RSTCTRL
PRCM Functional Description
•
PRCM Basic Programming Model
•
RM_RSTCTRL_ <domain_name> (Reset Control Register)
PRCM Register Manual
•
Global_Reg_PRM Register Summary
:
Table 3-457. PRM_RSTTIME
Address Offset
0x0000 0054
Physical Address
0x4830 7254
Instance
Global_Reg_PRM
Description
Reset duration control.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RSTTIME2
RSTTIME1
Bits
Field Name
Description
Type
Reset
31:13
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x00000
12:8
RSTTIME2
(Power domain) reset duration 2
RW
0x10
(number of RM_ICLK clock cycles)
7:0
RSTTIME1
(Global) reset duration 1
RW
0x06
(number of Func_32k.clk clock cycles)
Table 3-458. Register Call Summary for Register PRM_RSTTIME
PRCM Functional Description
•
•
•
:
•
:
PRCM Basic Programming Model
•
:
PRCM Register Manual
•
Global_Reg_PRM Register Summary
:
633
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated