sys_32k
vdds,
,
vdda_wkup_bg_bb
VDD3 voltage domain
vdd_core
vdd_mpu_iva
vdda_dpll_dll,
VDD4 voltage domain
VDD5 voltage domain
OSC_CLK
sys_nrespwron
sys_nreswarm_out
Global power on reset
Global warm reset
SYS_CLK
EFUSE_RSTPWRON
PRM_RSTPWRON
CM_SYS_CLK
CM_RSTPWRON_RET
DPLL3_ALWON_FCLK
L3_ICLK
CORE_RST
DPLL1_ALWON_FCLK
MPU_CLK
MPU_RST
Signal color-coding
PRCM input
PRCM output
Other
1
5
4
6
7
8
9
11 12
10
13
14
2
3
15
prcm-096
vdds_mem, vdda_sram
vdda_dpll_per
DPLL[1,2,3,4,5]_
RSTPWRON
Public Version
PRCM Functional Description
www.ti.com
3.5.1.9
Reset Sequences
3.5.1.9.1 Power-Up Sequence
shows the power-up sequence.
Figure 3-28. Power-Up Sequence
268
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated