PRCM
PRM
sys_nreswarm
Device
sys_nreswarm_in
sys_nreswarm_out
1.8 V
Pull-up
Reset
button
Reset to
peripherals
Global reset source
prcm-022
Public Version
www.ti.com
PRCM Functional Description
Table 3-21. EFUSE Power Domain Reset Signal
Name
I/O
(1)
Source
Reset Domain
EFUSE_RSTPWRON
I
PRCM
Resets the eFuse controller
(1)
I = Input; O = Output
This signal is asserted for any type of global cold reset and when the device wakes up from off mode.
3.5.1.5.14 BANDGAP Logic
The BANDGAP logic has one reset input signal (see
Table 3-22. BANDGAP Logic Reset Signal
Name
I/O
(1)
Source
Reset Domain
BANDGAP_RSTPWRON
I
PRCM
Resets the BANDGAP logic
(1)
I = Input; O = Output
This signal is asserted for any type of global cold reset and when the device wakes up from off mode.
3.5.1.5.15 External Warm Reset Assertion
shows the external warm reset interface.
Figure 3-23. External Warm Reset Interface
Any global reset source (internal or external) causes sys_nreswarm_out to be driven and maintained at
the boundary of the device for at least the amount of time configured in the PRCM.
[7:0]
RSTTIME1 bit field. This ensures that the device and its related peripherals are reset together.
NOTE:
Because the system warm-reset output is implemented on a bidirectional pad, any input
pulse on sys_nreswarm causes a global warm reset.
3.5.1.6
Reset Logging
A reset of the device is logged in two ways. First, dedicated registers in the PRCM module (the
RM_RSTST_power domain> and
registers) log the reset source. Second, the SCM logs the
device reset activity in dedicated registers.
3.5.1.6.1 PRCM Reset Logging Mechanism
The reset status registers (RM_RSTST_power domain> and
) are reset asynchronously on
assertion of a global cold reset. However, a reset status bit is always logged when the reset is released to
the domain.
259
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated