Public Version
PRCM Functional Description
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in this case, the initial sequence for device off-mode transition is the same as in
Device Off-Mode Transition Without Using SYS_OFF_MODE Signal, up to Step 8. After this, the following
steps are executed:
1. It shuts down the SRAM LDOs.
2. It asserts sys_off_mode. At this point, VDD1 and VDD2 are shut down.
3. It ramps down the wake-up LDO to 1 V.
4. It releases CLKREQ and disables the system clock oscillator (if used)
5. It waits for a wake-up event from the daisy chain.
3.5.7.4.2 Wake-Up Sequences
NOTE:
vdda_dpll_per and vdda_dpll_dll can be ramped up any time before VDD1 ramps up.
3.5.7.4.2.1 Device Wakeup from Off Mode Without Using the SYS_OFF_MODE Signal
On detection of a wake-up event from the daisy chain, the PRM performs the following steps:
1. It enables the system clock oscillator, asserts sys_clkreq, and ramps up the wake-up LDO.
2. It waits for the oscillator set-up time and the wake-up LDO stabilization time.
3. It sends the on command for VDD2 to the voltage controller. Through I2C4, the voltage controller
requests the power IC to set VDD2 to set the voltage corresponding to the
[31:24] ON bit field. (A legacy mode exists where vmode pins can be used
instead of I2C4, depending on the
[4] SEL_VMODE bit. In this case, the voltage
controller deasserts sys_nvmode2 and the power IC restores VDD2 to its previously programmed
value). At this point, VDD2 ramps up (the reset is not yet asserted on VDD2 logic).
4. It waits for the VDD2 regulator setup time counter to expire (
SETUPTIME2).
5. It sends the on command for VDD1 to the voltage controller. Through I2C4, the voltage controller
requests the power IC to set VDD1 to set the voltage corresponding to the
[31:24] ON bit field. (If vmode legacy mode is used, the voltage controller
deasserts sys_nvmode1 and the power IC restores VDD1 to its previously programmed value). At this
point, VDD1 ramps up (the reset is not yet asserted on VDD1 logic).
6. It waits for the VDD1 regulator setup time counter to expire (
[15:0] SETUPTIME1).
7. It restarts the memory LDOs.
8. It powers up all analog cells on the VDD2 domain and waits for the settling time of the LDO and analog
cells (internal counter).
9. The following steps can occur in parallel:
•
The DPLL, CORE, and MPU power domains are powered up.
•
The reset on the eFuse controller, DPLL, CORE, SR, and MPU power domains is asserted.
10. When the CORE, MPU, DPLLs, and SR are on, the PRM releases the eFuse controller reset, and the
eFuse scan starts.
11. When the scan completes, the DPLL resets are released. The DPLLs are in bypass and the clocks
start flowing (DPLL1 and DPLL3).
12. When the CORE and MPU domains are on, the PRM releases their corresponding domain output
isolations.
13. When the CORE power domain is on and DPLL3 is in bypass, the reset timer for the CORE power
domain starts.
14. When the MPU power domain is on and DPLL1 is in bypass, the reset timer for the MPU power
domain starts.
15. When the CORE reset time expires, the CORE domain reset is released.
16. When the CORE domain exits reset and the SCM context and I/O configuration are restored from
ScratchPad, memory starts.
17. When the PRM receives the acknowledge from the SCM, it releases the MPU and CORE domain
output isolations and the I/O isolation.
396
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated