Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
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Table 3-505. PRM_LDO_ABB_CTRL
Address Offset 0x0000 00F4
Physical Address 0x4830 72F4 Instance Global_Reg_PRM
Description This register allows the configuration of the ABB LDO (VDD1).
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SR2_WTCNT_VALUE RESERVED
SR2EN
RESERVED
ACTIVE_FBB_SEL
Bits Field Name Description Type Reset
31:16 RESERVED Write 0s for future compatibility. Read is undefined. R 0x0000
15:8 SR2_WTCNT_VALUE This value times 8 is used to set the ABB LDO settling RW 0x00
time to switch from the bypass mode to a Body-Bias
mode.
0x0: No wait-cycles are inserted.
7:3 RESERVED Write 0s for future compatibility. Read is undefined. R 0x00
2 ACTIVE_FBB_SEL Defines the ABB LDO mode when the voltage (VDD1) is RW 0x0
in fast OPP (OPP1G).
0x0: ABB LDO will operate in bypass mode.
0x1: ABB LDO will operate in FBB mode.
1 RESERVED Write 0s for future compatibility. Read is undefined. R 0X0
0 SR2EN Enables the ABB LDO. RW 0x0
0x0: ABB LDO is in bypass mode.
0x1: ABB LDO will operate in FBB mode or bypass mode
accordingly to the other SW settings and HW events.
Table 3-506. Register Call Summary for Register PRM_LDO_ABB_CTRL
PRCM Functional Description
• ABB LDOs Control : [0]
PRCM Register Manual
• Global_Reg_PRM Register Summary : [1]
3.8.2.14 NEON_PRM Registers
3.8.2.14.1 NEON_PRM Register Summary
Table 3-507. NEON_PRM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
RM_RSTST_NEON RW 32 0x0000 0058 0x4830 7358 C
PM_WKDEP_NEON RW 32 0x0000 00C8 0x4830 73C8 W
PM_PWSTCTRL_NEON RW 32 0x0000 00E0 0x4830 73E0 W
PM_PWSTST_NEON R 32 0x0000 00E4 0x4830 73E4 C
PM_PREPWSTST_NEON RW 32 0x0000 00E8 0x4830 73E8 C
650 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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