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PRCM Register Manual
Table 3-481. PRM_VP1_VSTEPMIN
Address Offset
0x0000 00B4
Physical Address
0x4830 72B4
Instance
Global_Reg_PRM
Description
This register allows the programming of the minimum voltage step and waiting time of the Voltage
Processor 1 (VDD1).
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
SMPSWAITTIMEMIN
VSTEPMIN
Bits
Field Name
Description
Type
Reset
31:24
RESERVED
Write 0s for future compatibility. Read is undefined.
R
0x00
23:8
SMPSWAITTIMEMIN
Slew rate for negative voltage step (in number of cycles
RW
0x0000
per step).
7:0
VSTEPMIN
Minimum voltage step
RW
0x00
Table 3-482. Register Call Summary for Register PRM_VP1_VSTEPMIN
PRCM Basic Programming Model
•
:
•
PRM_VP_VSTEPMIN (Voltage Processor Minimum Voltage Step)
PRCM Register Manual
•
Global_Reg_PRM Register Summary
:
Table 3-483. PRM_VP1_VSTEPMAX
Address Offset
0x0000 00B8
Physical Address
0x4830 72B8
Instance
Global_Reg_PRM
Description
This register allows the programming of the maximum voltage step and waiting time of the Voltage
Processor 1 (VDD1).
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
SMPSWAITTIMEMAX
VSTEPMAX
Bits
Field Name
Description
Type
Reset
31:24
RESERVED
Write 0s for future compatibility. Read is undefined.
R
0x00
23:8
SMPSWAITTIMEMAX
Slew rate for positive voltage step (in number of cycles
RW
0x0000
per step).
7:0
VSTEPMAX
Maximum voltage step
RW
0x00
Table 3-484. Register Call Summary for Register PRM_VP1_VSTEPMAX
PRCM Basic Programming Model
•
:
•
PRM_VP_VSTEPMAX (Voltage Processor Maximum Voltage Step)
PRCM Register Manual
•
Global_Reg_PRM Register Summary
:
643
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated