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PRCM Functional Description
The frequency of the processor clocks (MPU_CLK and IVA2_FCLK) must be configured according to the
selected OPP (the clock frequency associated with the operating voltage VDD1).
identifies the
clocks of the processors, their source clocks, and the configuration register bit fields.
Table 3-58. Processor Clock Configuration Controls
Module
Clocks
Reference
Multiplier
Divider (Factors)
Configuration Bits
Clock
(Factors)
DPLL1
CLKOUT
SYS_CLK
M (0 ... 2047)
MPU_DPLL_MULT
N (0 ... 127)
MPU_DPLL_DIV
MPU_CL
CLKOUTX2
M2
K
MPU_DPLL_CLKOUT_DIV
(1)
DPLL2
CLKOUT
SYS_CLK
M (0 ... 2047)
IVA2_DPLL_MULT
N (0 ... 127)
IVA2_DPLL_DIV
IVA2_CLK CLKOUT
M2 (1 ... 16)
IVA2_DPLL_CLKOUT_DIV
(1)
The MPU_CLK is generating the ARM_FCLK. ARM_FCLK is equal to the MPU_CLK. For information about ARM_FCLK, see
, MPU Subsystem.
Table 3-59. Processor Clock Configurations
DPLL State
BYPASS
LOCKED
MPU_CLK
DPLL1_FCLK (bypass clock from
(SYS_CLK * M * 2)/([N+1] * M2)
DPLL3)
ARM_FCLK
MPU_CLK
MPU_CLK
MPU subsystem internal module
ARM_FCLK/2
ARM_FCLK/2
clocks
3.5.3.8.2 Interface and Peripheral Functional Clock Configurations
The interface clock OPPs are identified as the pair of VDD2 operating voltage level and the device
interface clocks frequencies.
The DPLL3 (CORE DPLL) generates the CORE_CLK, which serves as the source clock for the L3_ICLK
and L4_ICLK interface clocks of the device. The CORE_CLOCK is also used by the DPLL1 and DPLL2 as
the bypass clock. The L3_ICLK is supplied to the SGX module as SGX_L3_ICLK and is used as its
interface clock. The L4_ICLK is used by RM_L4_CLK as its source clock.
The interface and peripheral functional clock frequencies can be configured according to the device
performance requirements for the OPP.
DPLL3 synthesized clock frequencies are configured as:
•
f
CLKOUT
= (f
SYS_CLK
x M)/(N+1)
•
f
CLKOUTX2
= f
CLKOUT
x 2
DPLL3 output clock frequencies are configured as:
•
f
CORE_CLK
= f
CLKOUT
/M2
•
f
COREX2_CLK
= f
CLKOUTX2
/M2
L3_ICLK, L4_ICLK and RM_L4_ICLK frequencies are configured as:
•
f
L3_ICLK
= f
CORE_CLK
/DIV_L3
•
f
L4_ICLK
= f
L3_ICLK
/DIV_L4
•
f
RM_L4_ICLK
= f
L4_ICLK
/DIV_RM
identifies the interface clocks, their reference clocks, and the control bits for configuration of
the interface clock frequencies.
351
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated