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PRCM Register Manual
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Table 3-109. CM_CLKSEL2_PLL_IVA2
Address Offset
0x0000 0044
Physical Address
0x4800 4044
Instance
IVA2_CM
Description
This register provides controls over the IVA2 DPLL.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
IVA2_DPLL_CLKOUT_DIV
Bits
Field Name
Description
Type
Reset
31:5
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x0000000
4:0
IVA2_DPLL_CLKOUT_DIV
IVA2 DPLL output clock divider factor (1 up to 16); Other
RW
0x01
enums: Reserved
0x1: DPLL2 CLKOUTX2 divided by 1
0x2: DPLL2 CLKOUTX2 divided by 2
0x3: DPLL2 CLKOUTX2 divided by 3
0x4: DPLL2 CLKOUTX2 divided by 4
0x5: DPLL2 CLKOUTX2 divided by 5
0x6: DPLL2 CLKOUTX2 divided by 6
0x7: DPLL2 CLKOUTX2 divided by 7
0x8: DPLL2 CLKOUTX2 divided by 8
0x9: DPLL2 CLKOUTX2 divided by 9
0xA: DPLL2 CLKOUTX2 divided by 10
0xB: DPLL2 CLKOUTX2 divided by 11
0xC: DPLL2 CLKOUTX2 divided by 12
0xD: DPLL2 CLKOUTX2 divided by 13
0xE: DPLL2 CLKOUTX2 divided by 14
0xF: DPLL2 CLKOUTX2 divided by 15
0x10: DPLL2 CLKOUTX2 divided by 16
Table 3-110. Register Call Summary for Register CM_CLKSEL2_PLL_IVA2
PRCM Functional Description
•
Processor Clock Configurations
PRCM Basic Programming Model
•
CM_CLKSELn_PLL_ <processor_name> (Processor DPLL Clock Selection Register)
:
PRCM Register Manual
•
464
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
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