Public Version
PRCM Functional Description
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3.5.3.8
Clock Configurations
The device supports several clock configurations. A clock configuration is a consistent set of divider ratios
programmed into the PRCM module to obtain a certain combination of clock speed to match the
performance requirement.
In the device, the MPU and IVA2.2 processors are connected to the interconnects through asynchronous
bridges. The functional frequency of these processors can be configured independently of their interface
clock frequency.
Therefore, the clock configurations of the device are split into two sections: one for device processor
clocks and one for device interface clocks.
An OPP of the device can be defined as a pair of device operating voltage and corresponding frequency.
The device processors are in the VDD1 voltage domain and the interface clocks are generated by the CM
clock generator in the VDD2 voltage domain. Hence, the OPPs of the processor clocks are identified for
the VDD1 voltage levels, independent of the interface clocks, which are associated with the VDD2 voltage
levels.
CAUTION
Clock configuration frequencies depend on the device operating voltage values.
3.5.3.8.1 Processor Clock Configurations
The processor OPPs are identified as the pair of VDD1 operating voltage level and processor clock
frequency.
Five generic processor OPPs can be defined as:
1. OPP1G2 (VDD1 = v3, (MPU_CLK = f
mpu
4, IVA2_CLK = f
iva
3))
2. OPP1G (VDD1 = v3, (MPU_CLK = f
mpu
3, IVA2_CLK = f
iva
3))
3. OPP130 (VDD1 = v2, (MPU_CLK = f
mpu
2, IVA2_CLK = f
iva
2))
4. OPP100 (VDD1 = v1 , (MPU_CLK = f
mpu
1, IVA2_CLK = f
iva
1))
5. OPP50 (VDD1 = v0 , (MPU_CLK = f
mpu
0, IVA2_CLK = f
iva
0))
where v3 > v2 > v1 > v0,
f
mpu
4 > f
mpu
3 > f
mpu
2 > f
mpu
1 > f
mpu
0,
f
iva
3 > f
iva
2 > f
iva
1 > f
iva
0 and
f
mpu
may not be equal to f
iva
NOTE:
OPP1G2 is available only for the OMAP3630-1200 device.
The clock configuration for the MPU and the IVA applies to the following clocks of the device:
•
DPLL1 (MPU DPLL) synthesized clock frequency (CLKOUT) configured by setting the M and N
parameters of the DPLL
•
DPLL1 (MPU DPLL) output clock frequency (MPU_CLK) configured by setting the M2 parameter of the
DPLL
NOTE:
The MPU_CLK is used to generate the ARM_FCLK. ARM_FCLK is equal to MPU_CLK (For
information about ARM_FCLK, see
, MPU Subsystem.)
•
DPLL2 (IVA2 DPLL) synthesized clock frequency (CLKOUT) configured by setting the M and N
parameters of the DPLL
•
DPLL2 (IVA2 DPLL) output clock frequency (IVA2_CLK) configured by setting the M2 parameter of the
DPLL
350
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
