Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 502 / 3738

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PRCM Register Manual
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Bits Field Name Description Type Reset
4 ST_12M_CLK Functional clock 12 MHz activity R 0x0
0x0: 12M_FCLK is not active
0x1: 12M_FCLK is active
3 ST_48M_CLK Functional clock 48 MHz activity R 0x0
0x0: 48M_FCLK is not active
0x1: 48M_FCLK is active
2 ST_96M_CLK Functional clock 96 MHz activity R 0x0
0x0: 96M_FCLK is not active
0x1: 96M_FCLK is active
1 ST_PERIPH_CLK DPLL4 clock activity R 0x0
0x0: DPLL4 is bypassed
0x1: DPLL4 is locked
0 ST_CORE_CLK DPLL3 clock activity R 0x0
0x0: DPLL3 is bypassed
0x1: DPLL3 is locked
Table 3-192. Register Call Summary for Register CM_IDLEST_CKGEN
PRCM Basic Programming Model
• DPLL Clock Control Registers : [0]
PRCM Register Manual
• Clock_Control_Reg_CM Register Summary : [1]
Table 3-193. CM_IDLEST2_CKGEN
Address Offset 0x0000 0024
Physical Address 0x4800 4D24 Instance Clock_Control_Reg_CM
Description This register allows monitoring the master clock activity. This register is read only and automatically
updated.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED
ST_120M_CLK
ST_PERIPH2_CLK
ST_FUNC120M_CLK
Bits Field Name Description Type Reset
31:4 RESERVED Read returns 0. R 0x0000000
3 ST_FUNC120M_CLK 120-MHz clock activity at the output stage of the DPLL5 R 0x0
0x0: DPLL5_M2_CLK is not active.
0x1: DPLL5_M2_CLK is active.
2 RESERVED Reserved for non-GP devices R 0x0
1 ST_120M_CLK USB HOST functional clock 120-MHz activity R 0x0
0x0: USB HOST 120M_FCLK is not active.
0x1: USB HOST 120M_FCLK is active.
0 ST_PERIPH2_CLK DPLL5 clock activity R 0x0
0x0: DPLL5 is bypassed.
0x1: DPLL5 is locked.
502 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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