Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
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Table 3-200. Register Call Summary for Register CM_CLKSEL1_PLL
PRCM Functional Description
• PRM Source-Clock Controls : [0]
• CM Source-Clock Controls : [1]
• Interface and Peripheral Functional Clock Configurations : [2] [3] [4]
PRCM Basic Programming Model
• CM_CLKSELn_PLL (DPLL Clock Selection Register) : [5]
PRCM Use Cases and Tips
• Switch VDD2 OPPs : [6] [7]
PRCM Register Manual
• Clock_Control_Reg_CM Register Summary : [8]
• Clock_Control_Reg_CM Registers :
Table 3-201. CM_CLKSEL2_PLL
Address Offset 0x0000 0044
Physical Address 0x4800 4D44 Instance Clock_Control_Reg_CM
Description This register controls the selection of the master clock frequencies.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SD_DIV DCO_SEL PERIPH_DPLL_MULT PERIPH_DPLL_DIV
RESERVED RESERVED
Bits Field Name Description Type Reset
31:24 SD_DIV This register bits field allows setting the sigma-delta RW 0x02
divider factor of the PERIPHERAL DPLL. It must be
comprise between 2 and 255. The values 0 and 1 are
reserved.
23:21 DCO_SEL This register bits field allows selecting the DCO used by RW 0x2
the PERIPHERAL DPLL to synthesize its output clock;
Other enums: Reserved
0x2: The lock frequency is comprised between 500 MHz
and 1000 MHz.
0x4: The lock frequency is comprised between 1000 MHz
and 2000 MHz.
20 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000
19:8 PERIPH_DPLL_MULT DPLL4 multiplier factor (0 to 4095) RW 0x000
7 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0
6:0 PERIPH_DPLL_DIV DPLL4 divider factor (0 to 127) RW 0x00
Table 3-202. Register Call Summary for Register CM_CLKSEL2_PLL
PRCM Functional Description
• DPLLs : [0] [1]
PRCM Basic Programming Model
• CM_CLKSELn_PLL (DPLL Clock Selection Register) : [2]
PRCM Register Manual
• Clock_Control_Reg_CM Register Summary : [3]
506 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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