Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Functional Description
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Table 3-45. Common PRM Source-Clock Gating Controls (continued)
Clock Name Reset Clock-Gating Control Gating Description
96M_ALWON_FCLK Gated CM_FCLKEN_PER [0] EN_MCBSP2, Gated when none of the three McBSPs
CM_FCLKEN_PER [1] EN_MCBSP3, [2..4] have their functional clock enable
CM_FCLKEN_PER [2] EN_MCBSP4, requested
CM_FCLKEN_SGX [1] EN_SGX
SGX_192M_FCLK Gated CM_FCLKEN_SGX [1] EN_SGX Active when SGX has its functional clock
enabled and its source is the 192MHz
clock
The oscillator output clock (OSC_SYS_CLK) is gated when the PRCM. PRM_CLKSRC_CTRL [4:3]
AUTOEXTCLKMODE bit field is programmed to power down the oscillator when the device enters
retention or off mode. In this condition, all the clock trees in the device must be gated, and the four DPLLs
(DPLL1, DPLL2, DPLL3, and DPLL4) must enter stop mode before this transition can occur.
SYS_CLK is gated under the same conditions as the oscillator output clock, but it is enabled only after the
oscillator stabilizes. Oscillator stabilization is determined by a counter overflow configured in the
PRCM.
PRM_CLKSETUP [15:0] SETUP_TIME bit field.
The sys_clkreq active condition is described in Section 3.5.3.5 , External Clock Control.
3.5.3.7.2 CM Source-Clock Controls
Figure 3-61 shows the common source-clock controls for the CM.
336 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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