Public Version
PRCM Register Manual
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Table 3-160. SGX_CM Register Summary
Register Name
Type
Register Width
Address Offset
Physical Address
Reset Type
(Bits)
RW
32
0x0000 0000
0x4800 4B00
W
RW
32
0x0000 0010
0x4800 4B10
W
R
32
0x0000 0020
0x4800 4B20
C
RW
32
0x0000 0040
0x4800 4B40
W
RW
32
0x0000 0044
0x4800 4B44
W
RW
32
0x0000 0048
0x4800 4B48
W
R
32
0x0000 004C
0x4800 4B4C
C
3.8.1.6.2 SGX_CM Registers
Table 3-161. CM_FCLKEN_SGX
Address Offset
0x0000 0000
Physical Address
0x4800 4B00
Instance
SGX_CM
Description
Controls the Graphic engine functional clock activity.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
EN_SGX
RESERVED
Bits
Field Name
Description
Type
Reset
31:2
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x00000000
1
EN_SGX
SGX functional clock enable
RW
0x0
0x0: SGX_FCLK is disabled
0x1: SGX_FCLK is enabled
0
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x0
Table 3-162. Register Call Summary for Register CM_FCLKEN_SGX
PRCM Functional Description
•
•
SGX Power Domain Clock Controls
:
PRCM Basic Programming Model
•
CM_FCLKEN_ <domain_name> (Functional Clock Enable Register)
:
PRCM Register Manual
•
:
488
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated