Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
Table 3-163. CM_ICLKEN_SGX
Address Offset 0x0000 0010
Physical Address 0x4800 4B10 Instance SGX_CM
Description Controls the Graphic engine interface clock activity.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
EN_SGX
Bits Field Name Description Type Reset
31:1 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
0 EN_SGX SGX interface clock control RW 0x0
0x0: SGX_L3_ICLK is disabled
0x1: SGX_L3_ICLK is enabled
Table 3-164. Register Call Summary for Register CM_ICLKEN_SGX
PRCM Functional Description
• SGX Power Domain Clock Controls : [0]
PRCM Basic Programming Model
• CM_ICLKEN_ <domain_name> (Interface Clock Enable Register) : [1]
PRCM Register Manual
• SGX_CM Register Summary : [2]
Table 3-165. CM_IDLEST_SGX
Address Offset 0x0000 0020
Physical Address 0x4800 4B20 Instance SGX_CM
Description SGX standby status. This register is read only and automatically updated.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
ST_SGX
Bits Field Name Description Type Reset
31:1 RESERVED Read returns 0 R 0x00000000
0 ST_SGX SGX standby status. R 0x1
0x0: SGX subsystem is active.
0x1: SGX subsystem is in standby mode.
Table 3-166. Register Call Summary for Register CM_IDLEST_SGX
PRCM Basic Programming Model
• CM_IDLEST_ <domain_name> (Idle-Status Register) : [0]
PRCM Register Manual
• SGX_CM Register Summary : [1]
489 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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