Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
Bits Field Name Description Type Reset
1:0 CLKTRCTRL_L3 Controls the clock state transition of the L3 clock domain. RW 0x0
0x0: Automatic transition is disabled
0x1: Reserved
0x2: Reserved
0x3: Automatic transition is enabled. Transition is
supervised by the HardWare.
Table 3-157. Register Call Summary for Register CM_CLKSTCTRL_CORE
PRCM Functional Description
• Sleep Dependencies :
PRCM Basic Programming Model
• CM_CLKSTCTRL_ <domain_name> (Clock State Control Register) : [1]
PRCM Register Manual
• CORE_CM Register Summary : [2]
Table 3-158. CM_CLKSTST_CORE
Address Offset 0x0000 004C
Physical Address 0x4800 4A4C Instance CORE_CM
Description This register provides a status on the interface clock activity in the domain.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
CLKACTIVITY_L4 CLKACTIVITY_L3
Bits Field Name Description Type Reset
31:2 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
1 CLKACTIVITY_L4 L4_ICLK interface clock activity status R 0x0
0x0: No domain interface clock activity
0x1: Domain interface clock is active
0 CLKACTIVITY_L3 L3_ICLK interface clock activity status R 0x0
0x0: No domain interface clock activity
0x1: Domain interface clock is active
Table 3-159. Register Call Summary for Register CM_CLKSTST_CORE
PRCM Functional Description
• Sleep Dependencies :
PRCM Basic Programming Model
• CM_CLKSTST_ <domain_name> (Clock State Status Register) : [1]
PRCM Register Manual
• CORE_CM Register Summary : [2]
3.8.1.6 SGX_CM Registers
3.8.1.6.1 SGX_CM Register Summary
487 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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