Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 361 / 3738

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PRCM Functional Description
Table 3-73. WKUP Power Domain Wake-Up Events (continued)
Internal Source PRCM Software Control Wake-Up Event Interrupt/Type Interrupt to
Wake-Up Module
Events
SmartReflex2 SmartRefle Yes No N/A
wakeup x2
GPTIMER1 GPTIMER1 Yes No N/A
wakeup
GPIO1 wakeup GPIO 1 PM_WKEN_WKUP Yes No N/A
NOTE: Some of the 32 I/O pins for the GPIO1 in the WKUP power domain are connected to the
device I/O pad logic in the CORE power domain (VDD2) and to the reset to the device I/O
pad logic in the WKUP power domain (VDD3). As a result, when the CORE power domain is
off, the corresponding I/O pins of the GPIO1 cannot generate a wake-up event. For details,
see
Chapter 25 , General-Purpose Interface Module.
3.5.4.5 Sleep and Wake-Up Dependencies
3.5.4.5.1 Sleep Dependencies
The (clock activity) dependencies between power domains are implemented to manage their sleep and
wake-up transitions to ensure stable operation of the device.
A power domain sleep transition is achieved when all its clock domains (that is, functional and interface)
are gated. For the gating of a clock domain, the following conditions must be satisfied:
•
All initiator modules in the clock domain are in standby mode, that is, they cannot initiate any new
transitions.
• All target modules in the clock domain are in idle mode and have no pending transitions.
• If the power domain depends on another power domain (that is, has a sleep dependency), the clock
domains of the other power domain must be muted.
A clock domain is said to be muted when all its public initiator modules (that is, the initiator modules of the
clock domain that can generate interconnect transactions towards targets outside the clock domain) are in
standby mode, and the domain cannot initiate new interconnect transactions toward other domains.
Table 3-74 describes the mute conditions for the clock domains.
Table 3-74. Clock Domain Mute Conditions
Clock Domain Name Clock Domain Composition Mute Conditions
MPU power domain and MPU INTC in
MPU MPU in stand-by, MPU INTC idle
CORE power domain
IVA2 power domain and WUGEN in
IVA2 IVA2.2 in stand-by, WUGEN idle
CORE power domain
SGX SGX power domain SGX in stand-by
CAM CAM power domain CAM in stand-by
DSS DSS power domain DSS in stand-by
PER PER power domain N/A (No public Initiator)
L3 interconnect, L3 targets/initiators in
CORE_L3 sDMA in standby
CORE power domain
L4 interconnect, L4 targets in CORE
CORE_L4 N/A (No public Initiator)
power domain
USBHOST USBHOST power domain USBHOST in stand-by
WKUP WKUP power domain N/A (No public Initiator)
361 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated