36-Mbit QDR™-II SRAM 2-Word
Burst Architecture
CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-12561 Rev. *D
Revised March 10, 2007
Features
■
Separate independent read and write data ports
❐
Supports concurrent transactions
■
267 MHz clock for high bandwidth
■
2-word burst on all accesses
■
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 534 MHz) at 267 MHz
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Single multiplexed address input bus latches address inputs
for both read and write ports
■
Separate port selects for depth expansion
■
Synchronous internally self-timed writes
■
QDR™-II operates with 1.5 cycle read latency when Delay Lock
Loop (DLL) is enabled
■
Operates like a QDR-I device with 1 cycle read latency in DLL
off mode
■
Available in x8, x9, x18, and x36 configurations
■
Full data coherency, providing most current data
■
Core V
DD
= 1.8V (±0.1V); IO V
DDQ
= 1.4V to V
DD
■
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
Variable drive HSTL output buffers
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1410JV18 – 4M x 8
CY7C1425JV18 – 4M x 9
CY7C1412JV18 – 2M x 18
CY7C1414JV18 – 1M x 36
Functional Description
The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and
CY7C1414JV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture consists
of two separate ports: the read port and the write port to access
the memory array. The read port has data outputs to support read
operations and the write port has data inputs to support write
operations. QDR-II architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common IO devices. Access to each
port is accomplished through a common address bus. The read
address is latched on the rising edge of the K clock and the write
address is latched on the rising edge of the K clock. Accesses to
the QDR-II read and write ports are completely independent of
one another. To maximize data throughput, both read and write
ports are provided with DDR interfaces. Each address location
is associated with two 8-bit words (CY7C1410JV18), 9-bit words
(CY7C1425JV18), 18-bit words (CY7C1412JV18), or 36-bit
words (CY7C1414JV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
267 MHz
250 MHz
Unit
Maximum Operating Frequency
267
250
MHz
Maximum Operating Current
x8
1330
1200
mA
x9
1330
1200
x18
1370
1230
x36
1460
1290
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