Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 325 / 3738

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PRCM Functional Description
NOTE: The system clock version provided to the DPLL4 can be pre-divided by a factor of 6.5
before feeding the DPLL4. This is done in the PRM through a dedicated programmable
register. This divider is intended to be used in case a 13-MHz system clock is used so that
the DPLL4 can be locked at 864 MHz.
3.5.3.4.2.2 Peripheral Module Clocks
Table 3-34 lists the peripherals, DSS, and CAM functional clock frequency requirements. These
frequencies must be operational over the full VDD2 voltage range.
Table 3-34. Peripheral Module Functional Clock Frequencies
Module Functional Clock Frequency
MMC-SDIO[1,2,3] 96M_FCLK 96 MHz
McBSP[1, 5] 96M_FCLK 96 MHz
CAM CAM_MCLK Up to 216 MHz
McSPI[1..4] CORE_48M_FCLK 48 MHz
UART[1..4]
Display subsystem DSS1_ALWON_FCLK Up to 173 MHz at nominal voltage
(OPP100), and up to 100 MHz at low
voltage (OPP50)
DSS2_ALWON_FCLK System clock
DSS_TV_FCLK 54 MHz
SGX SGX_FCLK Up to 200 MHz
I2C[1..3] CORE_96M_FCLK 96 MHz
HDQ CORE_12M_FCLK 12 MHz
GPTIMER1 GPT1_FCLK 32-kHz (p) or system clock
GPTIMER[2..9] GPTn_ALWON_FCLK 32-kHz (p) or system clock
GPTIMER[10, 11] GPTn_FCLK 32-kHz or system clock
ICR
WDTIMER2 WKUP_32K_FCLK 32 kHz
WDTIMER3 PER_32K_ALWON_FCLK 32 kHz
GPIO1 WKUP_32K_FCLK 32 kHz
GPIO[2-6] PER_32K_ALWON_FCLK 32 kHz
32-kHz sync timer 32K_FCLK 32 kHz (p)
Bandgap/temp sensor 32K_FCLK 32 kHz (p)
System control CORE_L4_ICLK L4_ICLK
3.5.3.5 External Clock Controls
Because the use of sys_32k and sys_altclk is described in Section 3.5.3.3.1 , PRM, and Section 3.5.3.3.2 ,
CM, these clock signals are not discussed here. This section discusses the remaining external clock
signals.
3.5.3.5.1 Clock Request (sys_clkreq) Control
The system clock request signal sys_clkreq is bidirectional.
In bypass mode in the system clock oscillator (see Section 3.5.3.5.2 ), it is an output signal driven by the
device to request an external clock. In this case, the output buffer is driven as long as the system clock is
requested by the device; otherwise, it remains in high impedance. In this way, other external peripherals
can share the same clock request signal with the device.
If the PRM_POLCTRL [1] CLKREQ_POL bit = 1, the software must configure the SCM to select the
internal pulldown on the sys_clkreq pad, or an external pulldown is connected to the pad.
325 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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