Public Version
PRCM Functional Description
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3.5.3.3.1 PRM
The PRM resides in the WKUP power domain. It handles the generation of the 32-kHz low-frequency
clocks and the high-frequency system clocks from the SYS_CLK. It also manages the clock oscillator and
the external clock output sys_clkout1.
SYS_CLK is generated by the internal oscillator or supplied as the external clock signal on the sys_xtalin
pin. It supplies most of the clocks in the device. Some of the device clocks sourced by SYS_CLK are
always powered (clocks are present even when the CORE power domain is in off state). SYS_CLK is also
the source of the WKUP power domain interface clocks.
It also handles the gating and distribution of the 96-MHz clock from DPLL4 to the CM and PER power
domain modules.
is a functional overview of the PRM. The other clocks in the figure are explained in the
following sections.
296
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
