DPLL4 power
domain
DPLL4_ALWON_FCLK
DPLL4
PRM
WKUP power domain
M2
M3
M4
M5
M6
CM
CORE power
domain
Ctrl
PRM_192M_ALWON_CLK
DPLL4_M3_CLK
DSS1_ALWON_FCLK
CAM_MCLK
EMU_PER_ALWON_CLK
prcm-041
Public Version
PRCM Functional Description
www.ti.com
•
The user must program the DPLL4 sigma-delta divider. This is done in
SD_DIV. This divider value is given by the following equation: SD_DIV = ceiling (CLKOUT/250), where
CLKOUT Is in MHz
NOTE:
Incorrect programming of the sigma-delta divider will lead to complete non-functionality or
poor performance.
The DPLL also provides an independent clock-gating signal for each of the six output clocks. The PRCM
module provides the DPLL with a clock-gating control signal, and the DPLL returns a clock activity status
signal indicating whether the output clock is effectively gated or running.
For an explanation of the DPLL multiplier, divider settings, and gating controls, see
, DPLL
Control.
Each clock-generating DPLL of the device has the following features:
•
Independent power domain
•
Control by the CM
•
Fed by always-on SYS_CLK with independent gating control for the SYS_CLK
•
Analog part supplied by a dedicated power supply (VDDPLL and VDDADAC at 1.8 V) and an
embedded LDO to eliminate 1-MHz noise
•
Up to five independent output dividers for simultaneous generation of multiple output clocks with
different frequencies
3.5.3.3.3.2.1 DPLL4 (Peripherals)
is a block diagram of DPLL4.
Figure 3-44. DPLL4 Clocks
DPLL4 receives its reference clock (DPLL4_ALWON_FCLK), which is the SYS_CLK from the PRM, and
can be divided before feeding the DPLL4. This is done in the PRM through dedicated programmable
306
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
