Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 338 / 3738

Hardware control
CORE_CLK
PRCM.CM_CLKSEL_CORE[3:2]
CLKSEL_L4
Ratios: 1/2
L3_ICLK
L4_ICLK
PRCM.CM_CLKSEL_WKUP[2:1]
CLKSEL_RM
Ratios: 1/2
RM_ICLK
PRCM.CM_CLKSEL_CORE[1:0]
CLKSEL_L3
Ratios: 1/2
prcm-058
Software control Source selection/division
L3X2_ICLK
Public Version
PRCM Functional Description
www.ti.com
Table 3-46 shows the common source-clock gating controls for the CM.
Table 3-46. Common CM Source-Clock Gating Controls
Clock Name Reset Clock-Gating Control Gating Description
CORE_CLK Running Depends on the clock-gating conditions of Gated when all interface clocks of the
L3_ICLK and L4_ICLK different modules of the device are gated
96M_FCLK Stopped Depends on the clock-gating conditions of If the dependent clocks are active, the clock
CORE_96M_FCLK is active.
48M_FCLK Stopped Depends on the clock-gating conditions of If the dependent clocks are active, the clock
CORE_12M_FCLK, PER_48M_FCLK and is active.
USBHOST_48M_FCLK
12M_FCLK Stopped Depends on the clock-gating conditions of If the dependent clock is active, the clock is
CORE_12M_FCLK active.
sys_clkout2 Stopped PRCM. CM_CLKOUT_CTRL [7] CLKOUT2_EN Active if enabled
DPLL4_M2_CLK Stopped Depends on the clock-gating conditions of: If the dependent clocks are active, the clock
96M_FCLK is active.
DPLL4_M3_CLK Stopped CM_CLKSEL1_PLL .SOURCE_54M and If the dependent clocks are active, the clock
depends on the clock-gating conditions of: is active. DSS_TV_CLK is a dependent
DPLL4_M2_CLK and DSS_TV_CLK clock if set by the register configuration.
120M_FCLK Stopped CM_FCLKEN_USBHOST [1] EN_USBHOST2, If any of the dependent clocks
CM_FCLKEN3_CORE [2] EN_USBTLL (CORE_120M_FCLK or
USBHOST_12M_FCLK) is active, the clock
is active.
3.5.3.7.3 Common Interface Clock Controls
Figure 3-62 shows the clock controls for the common interface.
Figure 3-62. Common Interface Clock Controls
Table 3-47 shows the clock-gating controls for the common interface.
Table 3-47. Common Interface Clock-Gating Controls
Clock Name Reset Clock-Gating Control Gating Description
L3X2_ICLK Running CORE_CLK gating conditions Depends on the gating conditions of the
CORE_CLK
L3_ICLK Running Depends on the clock-gating conditions of Gated when all L3 interface clocks of the
GFX_L3_ICLK, CORE_L3_ICLK, and different modules of the device are gated
CAM_L3_ICLK
L4_ICLK Running Depends on the clock-gating conditions of Gated when all L4 interface clocks of the
CORE_L4_ICLK, CAM_L4_ICLK, DSS_L4_ICLK, different modules of the device are gated
PER_L4_ICLK, SR_L4_ICLK, and
WKUP_L4_ICLK
RM_ICLK Running None Gated with source clock (CORE_CLK)
338 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated