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PRCM Register Manual
Bits
Field Name
Description
Type
Reset
31:5
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x0000000
4:0
DIV_120M
120 MHz clock divider factor M2 (1 up to 16); Other
RW
0x01
enums: Reserved
0x1: 120 MHz clock is DPLL5 clock divided by 1
0x2: 120 MHz clock is DPLL5 clock divided by 2
0x3: 120 MHz clock is DPLL5 clock divided by 3
0x4: 120 MHz clock is DPLL5 clock divided by 4
0x5: 120 MHz clock is DPLL5 clock divided by 5
0x6: 120 MHz clock is DPLL5 clock divided by 6
0x7: 120 MHz clock is DPLL5 clock divided by 7
0x8: 120 MHz clock is DPLL5 clock divided by 8
0x9: 120 MHz clock is DPLL5 clock divided by 9
0xA: 120 MHz clock is DPLL5 clock divided by 10
0xB: 120 MHz clock is DPLL5 clock divided by 11
0xC: 120 MHz clock is DPLL5 clock divided by 12
0xD: 120 MHz clock is DPLL5 clock divided by 13
0xE: 120 MHz clock is DPLL5 clock divided by 14
0xF: 120 MHz clock is DPLL5 clock divided by 15
0x10: 120 MHz clock is DPLL5 clock divided by 16
Table 3-208. Register Call Summary for Register CM_CLKSEL5_PLL
PRCM Basic Programming Model
•
CM_CLKSELn_PLL (DPLL Clock Selection Register)
PRCM Register Manual
•
Clock_Control_Reg_CM Register Summary
:
Table 3-209. CM_CLKOUT_CTRL
Address Offset
0x0000 0070
Physical Address
0x4800 4D70
Instance
Clock_Control_Reg_CM
Description
This register provides control over the SYS_CLKOUT2 output clock.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
CLKOUT2_EN
CLKOUT2_DIV
CLKOUT2SOURCE
Bits
Field Name
Description
Type
Reset
31:8
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x000000
7
CLKOUT2_EN
This bit controls the external output clock activity
RW
0x0
0x0: sys_clkout2 is disabled
0x1: sys_clkout2 is enabled
6
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x0
509
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
