Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Use Cases and Tips
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The OPP change-done interrupt of the voltage processor2 and the voltage processor bounds interrupt
of the SmartReflex2 module are enabled. The remaining interrupts of the voltage processor2 and
SmartReflex2 modules can be masked.
SR2. ERRCONFIG [22] VPBOUNDSINTENABLE 0x1 Enable the SmartReflex2 voltage processor interrupt.
PRCM. PRM_IRQENABLE_MPU 0x1 Enable the VP2 OPP change-done interrupt.
VP2_OPPCHANGEDONE_EN
The voltage processor2 and SmartReflex2 modules are enabled.
PRCM. PRM_VP2_CONFIG [0] VPENABLE 0x1 Enable the voltage processor module.
SR2. SRCONFIG [11] SR_EN 0x1 Enable the SmartReflex module.
The SmartReflex2 module sends the OPP change-done interrupt when the OPP change is complete
and the voltage is stable.
PRCM. PRM_IRQSTATUS_MPU [10] VP2_ Read On read, if this bit is 0x1, the OPP change is complete.
OPPCHANGEDONE_ST
PRCM. PRM_IRQSTATUS_MPU [10] VP2_ 0x1 Writing 0x1 clears the interrupt status bit.
OPPCHANGEDONE_ST
Enable the voltage processor2 interrupt for automatic SmartReflex2 operation.
SR2. ERRCONFIG [22] VPBOUNDSINTENABLE 0x1 Enable the voltage processor bounds interrupt.
After voltage switching is complete, the core frequencies must be switched. Thus, the DPLL3 output
divider is configured.
PRCM. CM_CLKSEL1_PLL [31:27] 0x1 Configure the DPLL3 output divider for OPP100 CORE_CLK
CORE_DPLL_CLKOUT_DIV frequency.
3.7.2 Voltage Control Using VMODE
3.7.2.1 Introduction
The PRCM module allows direct simple control of VDD1 and VDD2 through the dedicated signals
sys_nvmode1 and sys_nvmode2. A single voltage value can be linked in the external power IC to a given
state of sys_nvmode1 or sys_nvmode2. This allows direct voltage management (see
Table 3-94 ).
Table 3-94. VDD1 and VDD2 Voltage Control Through VMODE
sys_nvmode Signals Voltage Values Comments
sys_nvmode1 is high. VDD1 value 1 VDD1 value 1 depends on the power IC
programming.
sys_nvmode1 is low. VDD1 value 2 VDD1 value 2 depends on the power IC
programming.
sys_nvmode2 is high. VDD2 value 1 VDD2 value 1 depends on the power IC
programming.
sys_nvmode2 is low. VDD2 value 2 VDD2 value 2 depends on the power IC
programming.
NOTE: The polarity of sys_nvmode1 and sys_nvmode2 is programmable. This means that the
PRCM module sets them high or low, depending on the user settings. For this reason, the
external power IC must be configured to provide a given voltage level depending on the
states of the sys_nvmodex signals.
Assertion of sys_nvmode1 and sys_nvmode2 (low or high, depending on the chosen polarity) occurs
immediately after a device sleep or wake-up transition. When the PRCM module triggers a sleep transition
(ON to OFF, or ON to retention), it deasserts sys_nvmode1 and sys_nvmode2. When the PRCM module
detects a device wake-up transition (retention to on, or off to on), it asserts sys_nvmode1 and
sys_nvmode2.
456 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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