Public Version
PRCM Register Manual
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Table 3-186. Clock_Control_Reg_CM Register Summary (continued)
Register Name
Type
Register Width
Address Offset
Physical Address
Reset Type
(Bits)
RW
32
0x0000 0070
0x4800 4D70
C
3.8.1.8.2 Clock_Control_Reg_CM Registers
Table 3-187. CM_CLKEN_PLL
Address Offset
0x0000 0000
Physical Address
0x4800 4D00
Instance
Clock_Control_Reg_CM
Description
This register allows controlling the DPLL3 and DPLL4 modes.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PWRDN_TV
PWRDN_96M
PWRDN_CAM
PWRDN_DSS1
EN_CORE_DPLL
EN_PERIPH_DPLL
PWRDN_EMU_CORE
PWRDN_EMU_PERIPH
EN_CORE_DPLL_LPMODE
EN_PERIPH_DPLL_LPMODE
EN_CORE_DPLL_DRIFTGUARD
EN_PERIPH_DPLL_DRIFTGUARD
Bits
Field Name
Description
Type
Reset
31
PWRDN_EMU_PERIPH
This bit allows to power-down or not the DPLL4_M6_CLK
RW
0x0
HSDIVIDER path.
0x0: Power-up the DPLL4_M6_CLK HSDIVIDER path.
0x1: Power-down the DPLL4_M6_CLK HSDIVIDER path.
Writting this bit to 1 will take effect immediatly.
30
PWRDN_CAM
This bit allows to power-down or not the DPLL4_M5_CLK
RW
0x0
HSDIVIDER path.
0x0: Power-up the DPLL4_M5_CLK HSDIVIDER path.
0x1: Power-down the DPLL4_M5_CLK HSDIVIDER path.
Writting this bit to 1 will take effect immediatly.
29
PWRDN_DSS1
This bit allows to power-down or not the DPLL4_M4_CLK
RW
0x0
HSDIVIDER path.
0x0: Power-up the DPLL4_M4_CLK HSDIVIDER path.
0x1: Power-down the DPLL4_M4_CLK HSDIVIDER path.
Writting this bit to 1 will take effect immediatly.
28
PWRDN_TV
This bit allows to power-down or not the DPLL4_M3_CLK
RW
0x0
HSDIVIDER path.
0x0: Power-up the DPLL4_M3_CLK HSDIVIDER path.
0x1: Power-down the DPLL4_M3_CLK HSDIVIDER path.
Writting this bit to 1 will take effect immediatly.
27
PWRDN_96M
This bit allows to power-down or not the DPLL4_M2_CLK
RW
0x0
path.
0x0: Power-up the DPLL4_M2_CLK path.
0x1: Power-down the DPLL4_M2_CLK path. Writting this
bit to 1 will take effect immediatly.
498
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated