Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
Table 3-190. Register Call Summary for Register CM_CLKEN2_PLL
PRCM Functional Description
• DPLL Modes : [1]
• DPLL Low-Power Mode : [2]
• Recalibration : [3]
• DPLL Source-Clock Controls : [4]
PRCM Register Manual
• Clock_Control_Reg_CM Register Summary : [5]
Table 3-191. CM_IDLEST_CKGEN
Address Offset 0x0000 0020
Physical Address 0x4800 4D20 Instance Clock_Control_Reg_CM
Description This register allows monitoring the master clock activity. This register is read only and automatically
updated.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED
ST_TV_CLK
ST_54M_CLK ST_12M_CLK ST_48M_CLK ST_96M_CLK
ST_CAM_CLK
ST_DSS1_CLK
ST_CORE_CLK
ST_PERIPH_CLK
ST_FUNC96M_CLK
ST_EMU_CORE_CLK
ST_EMU_PERIPH_CLK
Bits Field Name Description Type Reset
31:14 RESERVED Read returns 0. R 0x00000
13 ST_EMU_PERIPH_CLK Emulation clock activity at the output stage of the DPLL4 R 0x0
0x0: EMU_PER_ALWON_CLK is not active
0x1: EMU_PER_ALWON_CLK is active
12 ST_CAM_CLK CAMERA functional clock activity at the output stage of R 0x0
the DPLL4
0x0: CAM_MCLK is not active
0x1: CAM_MCLK is active
11 ST_DSS1_CLK DSS functional clock 1 activity at the output stage of the R 0x0
DPLL4
0x0: DSS1_ALWON_FCLK is not active
0x1: DSS1_ALWON_FCLK is active
10 ST_TV_CLK TV clock activity at the output stage of the DPLL4 R 0x0
0x0: DPLL4_M3_CLK is not active
0x1: DPLL4_M3_CLK is active
9 ST_FUNC96M_CLK 96 MHz clock activity at the output stage of the DPLL4 R 0x0
0x0: DPLL4_M2_CLK is not active
0x1: DPLL4_M2_CLK is active
8 ST_EMU_CORE_CLK Emulation clock activity at the output stage of the DPLL3 R 0x0
0x0: EMU_CORE_ALWON_CLK is not active
0x1: EMU_CORE_ALWON_CLK is active
7:6 RESERVED Read returns 0. R 0x0
5 ST_54M_CLK Functional clock 54 MHz activity R 0x0
0x0: 54MHz clock is not active
0x1: 54MHz clock is active
501 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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