Public Version
PRCM Register Manual
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Table 3-188. Register Call Summary for Register CM_CLKEN_PLL (continued)
PRCM Basic Programming Model
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Enabling and Disabling the Functional Clocks
PRCM Register Manual
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Clock_Control_Reg_CM Register Summary
:
Table 3-189. CM_CLKEN2_PLL
Address Offset
0x0000 0004
Physical Address
0x4800 4D04
Instance
Clock_Control_Reg_CM
Description
This register controls the DPLL5 modes.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
EN_PERIPH2_DPLL
EN_PERIPH2_DPLL_LPMODE
EN_PERIPH2_DPLL_DRIFTGUARD
Bits
Field Name
Description
Type
Reset
31:11
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x000000
10
EN_PERIPH2_DPLL_LPMODE
This bit allows to enable or disable the LP mode of the
RW
0x0
DPLL5. Writting this bit to switch the mode between LP
or normal mode will take effect only when the DPLL will
have transition into the bypass or stop state, followed by
a lock or re-lock of the DPLL.
0x0: Disables the DPLL LP mode to re-enter the normal
mode at the following lock or re-lock sequence.
0x1: Enables the DPLL LP mode to enter the LP mode at
the following lock or re-lock sequence.
9:8
RESERVED
RW
0x0
7:4
RESERVED
Reserved
RW
0x1
3
EN_PERIPH2_DPLL_DRIFTGUA This bit allows to enable or disable the automatic
RW
0x0
RD
recalibration feature of the DPLL5. The DPLL5 will
automatically start a recalibration process upon assertion
of the recal flag if this bit is set.
0x0: Disables the DPLL5 automatic recalibration mode
0x1: Enables the DPLL5 automatic recalibration mode
2:0
EN_PERIPH2_DPLL
DPLL5 control; Other enums: Reserved
RW
0x1
0x1: Put the second DPLL5 in low power stop mode
0x7: Enables the DPLL5 in lock mode
500
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated