On
Retention
SYS_CLK
sys_nvmode2
VDD2
Device state
OPP100
LOW
0 V
On
1
2
prcm-076
Public Version
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PRCM Functional Description
CAUTION
It is highly recommended to use the embedded dedicated I2C4 instead of
VMODE, which is a legacy mode. The I2C4 provides greater flexibility and
higher efficiency in terms of power optimization.
3.5.6.5
VDD1 and VDD2 Control
The main power-supply sources, VDD1 and VDD2, can be controlled using mutually exclusive modes
specified in the SCM:
•
Direct control with VMODE signals or I2C interface
•
Dedicated SmartReflex I
2
C control
Because both control modes are multiplexed on the same device pins, direct control signals can be used
alternately with I
2
C control signals. The muxes are managed by the SCM.
3.5.6.5.1 Direct Control With VMODE Signals
In direct-control mode, the VDD1 and VDD2 voltage sources can be controlled by the voltage FSMs in the
PRM to trigger a voltage transition based on the power domain states. The voltage FSMs use a VMODE
interface to send voltage commands through the sys_nvmode1 and sys_nvmode2 pins of the device to
the external power IC. The simple voltage-control commands of the VMODE interface can be used to set
two voltage values (VDD1 and VDD2) per voltage domain .
The sys_nvmode[1,2] signals request new voltage levels to the external SMPS. The polarity of the
sys_nvmode[1,2] signals from the PRM is configured by the PRCM.
[0] EXTVOL_POL bit,
which is active-low by default. When the signal goes low, a lower voltage is supplied, and when it goes
high, a higher voltage is supplied.
The VMODE voltage control is enabled by setting the PRM.
[4] SEL_VMODE bit, and is
triggered when the device switches between low-power (retention or off) mode and normal (on) mode.
is an example of a VDD2 voltage transition from an operational voltage (OPP100) to the
lowest functional voltage of the device (LOW). In this example, the PRCM module is programmed to
automatically lower sys_nvmode2 when the device enters sleep mode. The power IC is programmed to
ramp the VDD2 voltage down to LOW when sys_nvmode2 is deasserted and to ramp up the voltage to
OPP100 when sys_nvmode2 is asserted. The PRCM module must also wait for the VDD2 regulator to
stabilize when sys_nvmode2 is deasserted and asserted. This stabilization time is programmable by
software using the PRCM.
register.
Figure 3-81. Voltage Transition Controlled by sys_nvmode2
Internally, the PRM manipulates two logical voltage levels (L0 and L1) for each sys_nvmode[1,2] signal.
One level is set when all the power domains in the voltage domain are in retention or off mode, while the
other is set when a power domain is on. The power IC must be configured to switch to low voltage when
the associated sys_nvmode[1,2] signal is received, and vice versa.
379
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
