Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
Table 3-118. CM_SYSCONFIG
Address Offset 0x0000 0010
Physical Address 0x4800 4810 Instance OCP_System_Reg_CM
Description This register controls the various parameters of the interface clock
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
AUTOIDLE
Bits Field Name Description Type Reset
31:1 RESERVED Write 0s for future compatibility. Reads returns 0. R 0x00000000
0 AUTOIDLE Internal clock gating strategy (for the CM part of the RW 0x1
PRCM)
0x0: Interface clock is free-running
0x1: Automatic clock gating strategy is enabled, based on
the interface activity.
Table 3-119. Register Call Summary for Register CM_SYSCONFIG
PRCM Basic Programming Model
• PRCM Configuration Registers : [0]
PRCM Register Manual
• OCP_System_Reg_CM Register Summary : [1]
3.8.1.4 MPU_CM Registers
3.8.1.4.1 MPU_CM Register Summary
Table 3-120. MPU_CM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
CM_CLKEN_PLL_MPU RW 32 0x0000 0004 0x4800 4904 W
CM_IDLEST_MPU R 32 0x0000 0020 0x4800 4920 C
CM_IDLEST_PLL_MPU R 32 0x0000 0024 0x4800 4924 C
CM_AUTOIDLE_PLL_MPU RW 32 0x0000 0034 0x4800 4934 W
CM_CLKSEL1_PLL_MPU RW 32 0x0000 0040 0x4800 4940 W
CM_CLKSEL2_PLL_MPU RW 32 0x0000 0044 0x4800 4944 W
CM_CLKSTCTRL_MPU RW 32 0x0000 0048 0x4800 4948 W
CM_CLKSTST_MPU R 32 0x0000 004C 0x4800 494C C
3.8.1.4.2 MPU_CM Registers
467 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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