Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 2807 / 3738

Start
No
Yes
End
Clear XDR bit
(see Note 1)
Read
I2C .I2C_STAT i
register
Is bus
free?
Write I2C .I2C_CON with 8603h or 8601h i
(F/S mode) or with 9603h or 9601h (HS
mode)
Read I2C .I2C_STAT i
register and save value
I2C .I2C_STAT[1] i
NACK bit = 0?
No
No No
No Yes
Yes
Yes Yes
Is ACK
returned
(NACK=0)?
Is
arbitration
lost (AL=1)?
Can
update the
registers
(ARDY=1)?
I2C .I2C_STAT[0] AL i
bit = 1?
I2C .I2C_STAT[2] i
ARDY bit = 1?
I2C .I2C_STAT[14] i
XDR bit = 1?
Is
send data required
to end transfer
(XDR=1)?
Decisions
based on the
saved value of
I2C .I2C_STAT
i
register
[EXPECTED COMMAND SEQUENCE]
- Full transfer
(I2C .I2C_CON[0] STT bit; I2C .I2C_CON[1] STP bit) = (1;1)
i i
- 2 phases transfer
(I2C .I2C_CON[0] STT bit; I2C .I2C_CON[1] STP bit) = (1;0), and then (0;1)
i i
- Multiple phases transfer
(I2C .I2C_CON[0] STT bit; I2C .I2C_CON[1] STP bit) = (1;0), (1;0)....and then (0;1) or (1;1)
i i
[EXPECTED I2C_IE] I2C .I2C_IE = 4007h i
Read I2C .I2C_BUFSTAT[5:0]
i
TXSTAT to check the amount of
data left to be transmitted
Clear ARDY bit
(see Note 1)
Clear AL bit
(see Note 1)
Clear NACK bit
(see Note 1)
Transfer the amount of data left by writing
I2C .I2C_DATA register for I2C.I2C_BUFSTAT[5:0] i
TXSTAT times or by activating the draining feature
of the DMA controller
I2C .I2C_CON[0] STT and i
I2C .I2C_CON[1] STP and
i
I2C .I2C_CON[10] MST bits i
are cleared by hardware
I2C .I2C_CON[0] STT and i
I2C .I2C_CON[1] STP bits i
are cleared by hardware
Reprogram the
registers
(see Note 2)
New start?
Yes
No
Hardware releases the serial
clock line (i2c _scl) to high i
I C controller goes into
2
slave receiver mode.
Stop?
Yes
Is
interrupt
received?
Yes
No Take necessary
action (DMA serves
the request
Is
DMA request
received?
Yes
No
I2C .I2C_STAT[12] BB bit = 0? i
Set appropriate value to every bit of I2C .12C_CON register. i
I2C .I2C_CON[15] I2C_EN bit must be set to 1 to take the I C controller i
2
out of reset.
Setting this bit and setting other mode bits can be done simultaneously.
No
i2c-033
Public Version
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HS I
2
C Basic Programming Model
Figure 17-33. HS I
2
C Master Transmitter Mode, DMA Method in F/S and HS Modes (I
2
C Mode)
(1) The NACK, AL, ARDY, and XDR bits are cleared by writing 1 to each corresponding bit in the I2Ci. I2C_STAT
register.
(2) Reprogram registers means: I2Ci. I2C_CON [11] STB and/or I2Ci. I2C_CON [10] MST bit and/or
I2Ci. I2C_SA [9:0] SA register and/or I2Ci. I2C_CNT [15:0] DCOUNT register and/or I2Ci. I2C_CON [0] STT bit
and/or I2Ci. I2C_CON [1] STP bit.
NOTE: In HS mode, the Sr condition and the clock frequency switching are automatically generated
by the multimaster HS I
2
C controller.
2807 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
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