Public Version
UART/IrDA/CIR Register Manual
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
IRRXINVERT
UART_PULSE
SET_TXIR_ALT
STS_FIFO_TRIG
IRTX_UNDERRUN
CIR_PULSE_MODE
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Read returns 0x00.
R
0x00
7
SET_TXIR_ALT
Provide alternate functionnality for MDR1[4] (SET_TXIR)
RW
0
0x0:
Normal mode.
0x1:
Alternate mode for SET_TXIR.
6
IRRXINVERT
Only for IR mode (IrDA and CIR). Invert RX pin in the
RW
0
module before the voting or sampling system logic of the
infrared block. This does not affect the RX path in UART
modem modes.
0x0:
Inversion is performed.
0x1:
No inversion is performed.
5:4
CIR_PULSE_ MODE
CIR pulse modulation definition. Defines high level of the
RW
0x00
pulse width associated with a digit:
0x0:
Pulse width of 3 from 12 cycles
0x1:
Pulse width of 4 from 12 cycles
0x2:
Pulse width of 5 from 12 cycles
0x3:
Pulse width of 6 from 12 cycles
3
UART_PULSE
UART mode only. Used to allow pulse shaping in UART
RW
0
mode.
0x0:
Normal UART mode
0x1:
UART mode with pulse shaping
2:1
STS_FIFO_TRIG
Only for IR-IrDA mode
RW
0x00
Frame status FIFO threshold select:
0x0:
1 entry
0x1:
4 entries
0x2:
7 entries
0x3:
8 entries
0
IRTX_UNDERRUN
IrDA transmission status interrupt. When the
R
0
interrupt occurs, the meaning of the interrupt is:
0x0:
The last bit of the frame was transmitted
successfully without error.
0x1:
An underrun occurred. The last bit of the frame
was transmitted but with an underrun error. The
bit is reset to 0 when the
register
is read.
Table 19-82. Register Call Summary for Register MDR2_REG
UART/IrDA/CIR Environment
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UART/IrDA/CIR Functional Description
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UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
[8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25]
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2954UART/IrDA/CIR
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated