Texas Instruments OMAP36 Series, Technical Reference Manual

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Source selection/division Hardware control Software control
SR_ALWON_FCLK
PRCM.CM_FCLKEN_WKUP[6]
EN_SR1
PRCM.CM_FCLKEN_WKUP[7]
EN_SR2
GC
SYS_CLK
SR_L4_ICLK
CL
L4_ICLK
prcm-070
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PRCM Functional Description
Table 3-56. PER Power Domain Clock-Gating Controls
Clock Name Reset Clock-Gating Control Gating Description
PER_48M_FCLK Stopped PRCM. CM_FCLKEN_PER EN_UART[3-4] Gated when the enable bit is set to 0
PER_96M_FCLK Stopped McBSP[2..4] input clock source select (in SCM) Gated when the enable bits of the module
and PRCM. CM_FCLKEN_PER EN_MCBSP[2-4] functional clock are set to 0 (the McBSPs can
and the DPLL4 operating mode have MCBSP_CLKS as an alternate
functional clock) or DPLL4 is in stop or
bypass mode
MCBSP_CLKS Stopped See Chapter 13 , System Control Module.
PER_32K_ALWON_ Stopped PRCM. CM_FCLKEN_PER EN_GPIO[2-6] and Gated when all the enable bits are set to 0
FCLK PRCM. CM_FCLKEN_PER [12] EN_WDT3
GPT2_ALWON_FCLK Stopped PRCM. CM_FCLKEN_PER [3] EN_GPT2 Gated when the enable bit is set to 0
GPT3_ALWON_FCLK Stopped PRCM. CM_FCLKEN_PER [4] EN_GPT3 Gated when the enable bit is set to 0
GPT4_ALWON_FCLK Stopped PRCM. CM_FCLKEN_PER [5] EN_GPT4 Gated when the enable bit is set to 0
GPT5_ALWON_FCLK Stopped PRCM. CM_FCLKEN_PER [6] EN_GPT5 Gated when the enable bit is set to 0
GPT6_ALWON_FCLK Stopped PRCM. CM_FCLKEN_PER [7] EN_GPT6 Gated when the enable bit is set to 0
GPT7_ALWON_FCLK Stopped PRCM. CM_FCLKEN_PER [8] EN_GPT7 Gated when the enable bit is set to 0
GPT8_ALWON_FCLK Stopped PRCM. CM_FCLKEN_PER [9] EN_GPT8 Gated when the enable bit is set to 0
GPT9_ALWON_FCLK Stopped PRCM. CM_FCLKEN_PER [10] EN_GPT9 Gated when the enable bit is set to 0
PER_L4_ICLK Stopped PRCM. CM_ICLKEN_PER EN_(GPIO[2..6], Gated when:
WDT3, UART[3, 4], GPT[2..9], MCBSP[2..4]) and
• All enable bits are set to 0.
PRCM. CM_AUTOIDLE_PER AUTO_(GPIO[2..6],
• All enable-autoidle bit pairs are set to 1,
WDT3, UART[3, 4], GPT[2..9], and MCBSP[2..4])
and the clock is not requested by any
module.
96M_ALWON_FCLK Stopped None Always-on clock
For audio applications, the McBSP functional clocks are provided externally by the MCBSP_CLKS pin.
This clock must be permanently supplied, to let McBSPs function when the CORE power domain is in the
off power state. If the external clock input is selected as the functional clock, the PER power domain sleep
transition is prevented.
3.5.3.7.13 SMARTREFLEX Power Domain Clock Controls
Figure 3-74 shows the clock controls for the SMARTREFLEX power domain. Table 3-57 lists the
clock-gating controls for the SMARTREFLEX power domain.
Figure 3-74. SMARTREFLEX Power Domain Clock Controls
Table 3-57. SMARTREFLEX Power Domain Clock-Gating Controls
Clock Name Reset Clock-Gating Control Gating Description
SR_ALWON_FCLK Stopped PRCM. CM_FCLKEN_WKUP [6] EN_SR1 and Gated when both enable bits are set to 0
PRCM. CM_FCLKEN_WKUP [7] EN_SR2
SR_L4_ICLK Running Depends on L4_ICLK activity (hardware control)
349 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated