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Camera ISP Basic Programming Model
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IF (
[15] BUSYAF == 0 OR
[18] BUSYAEAWB == 0) OR IF (EOF interrupt occurs)
DISABLE AF or AE/AWB
CHANGE REGISTERS AF or AE/AWB
ENABLE AF or AE/AWB
6.5.9.5
Camera ISP H3A Interframe Operations
Between frames, it may be necessary to modify the memory pointers before processing the next frame.
Since the
and memory pointer registers are shadowed, these modifications can occur any time
before the end of the frame, and the data is latched in for the next frame. The MPU subsystem can
perform these changes on receiving an interrupt.
6.5.9.6
Camera ISP H3A Summary of Constraints
The following is a list of register configuration constraints to adhere to when programming the H3A. It can
be used as a quick checklist. More detailed register setting constraints can be found in the individual
register descriptions.
•
The output addresses must be on 64-byte boundaries.
AF Engine:
•
The paxel horizontal start value must be greater than or equal to the IIR horizontal start position.
•
The width and height of the paxels must be even numbers.
•
The minimum width of the autofocus paxel must be 16 pixels.
•
Paxels cannot overlap the last pixel in a line.
•
Paxels must be adjacent to one another.
AEW Engine:
•
The width and height of the windows must be even numbers.
•
Subsampling windows can only start on even numbers.
•
The minimum width of the AE/AWB windows is 6 pixels.
6.5.10 Programming the Histogram
This section discusses issues related to software control of the histogram module. It lists which registers
are required to be programmed in different modes, how to enable and disable the histogram, and how to
check the status of the histogram; discusses the different register access types; and enumerates
programming constraints.
6.5.10.1 Camera ISP Histogram Setup/Initialization
This section discusses the configuration of the histogram required before image processing can begin.
6.5.10.1.1 Camera ISP Histogram Reset Behavior
On hardware reset of the camera ISP, all registers in the histogram are reset to their reset values.
However, since the histogram output memory is stored in internal memory, its contents do not have reset
values. If the reset is a chip-level power-on reset (reset after power is applied), the contents of this
memory are unknown. If the reset is a camera ISP module reset (when power remains active), the
contents of this memory remain the same as before the reset.
6.5.10.1.2 Camera ISP Histogram Reset of Histogram Output Memory
Clear the output memory before enabling the histogram. This can be done two ways:
•
Writing zeros to the memory through software
•
If the
[7] CLR bit is set, reading the memory causes it to be reset after the read.
Reads and writes to the output memory are blocked when the
[1] BUSY bit is 1.
1292
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
