Public Version
www.ti.com
L3 Interconnect
Bits
Field Name
Description
Type
Reset
63:32
Reserved
Reserved
R
0x00000000
31
MULTI
Multiple errors
RW1toClr
0
0x0:Multiple errors not seen
0x1:Multiple errors seen
30
SECONDARY
Secondary error present
RW1toClr
0
29:28
Reserved
Reserved
R
0x0
27:24
CODE
Error Code see
RW1toClr
0x0
23:21
Reserved
Reserved
R
0x0
20:16
REQ_INFO
MReqInfo bits of command selected for protection checking see
R
0x00
15:8
INITID
Initiator ID from which the command was launched see
R
0x00
7
Reserved
Reserved
R
0
6:4
REGION
Protection region number that command mapped to
R
0x0
3
Reserved
Reserved
R
0
2:0
CMD
Command that caused the error see
R
0x0
Table 9-79. Register Call Summary for Register L3_PM_ERROR_LOG
L3 Interconnect
•
L3 Firewall Error-Logging Registers
•
:
•
:
•
:
Table 9-80. L3_PM_CONTROL
Address Offset
0x28
Physical Address
See
to
Description
This register controls protection mechanism functions such as error reporting.
Type
RW
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
ERROR_REP
ERROR_SECONDARY_REP
Bits
Field Name
Description
Type
Reset
63:26
Reserved
Reserved
R
0x0000000000
25
ERROR_SECONDARY_REP
Out of band error reporting
RW
1
0x0: Out of band error reporting suppress
0x1: Out of band error report
24
ERROR_REP
Out of band error reporting
RW
1
2045
SWPU177N – December 2009 – Revised November 2010
Interconnect
Copyright © 2009–2010, Texas Instruments Incorporated