MUX
prcm-046
96M_FCLK
48M_FCLK
12M_FCLK
L4_ICLK
CM_32K_CLK
CM_SYS_CLK
MCBSP_CLKS
CM
CORE power domain
HDQ/1-wire
MUX
UART[1, 2]
I2C[1, 2, 3]
McSPI[1–4]
McBSP[1, 5]
C
O
R
E
_
9
6
M
_
F
C
L
K
C
O
R
E
_
4
8
M
_
F
C
L
K
C
O
R
E
_
1
2
M
_
F
C
L
K
C
O
R
E
_
L
4
_
IC
L
K
GPT10_FCLK
GPT11_FCLK
PRM
MUX
From system
control module
EMU async
bridge
MMC[1, 2, 3]
Wake-up power domain
GPTIMER
[10, 11]
Temp. sensor (x2)
USB TLL
USBTLL_SAR_FCLK
120M_FCLK
C
O
R
E
_
1
2
0
M
_
F
C
L
K
C
O
R
E
_
3
2
K
_
F
C
L
K
Public Version
www.ti.com
PRCM Functional Description
Figure 3-49. CORE Clock Signals: Part 2
313
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
