Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
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Bits Field Name Description Type Reset
31:8 RESERVED Write 0s for future compatibility. Read returns 0. R 0x000000
7 CLKOUT_EN This bit controls the external output clock (sys_clkout1) RW 0x1
activity
0x0: sys_clkout1 is disabled
0x1: sys_clkout1 is enabled
6:0 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00
Table 3-389. Register Call Summary for Register PRM_CLKOUT_CTRL
PRCM Functional Description
• External Output Clock1 (sys_clkout1) Control : [0] [1]
• PRM Source-Clock Controls : [2]
PRCM Register Manual
• Clock_Control_Reg_PRM Register Summary : [3]
3.8.2.9 DSS_PRM Registers
3.8.2.9.1 DSS_PRM Register Summary
Table 3-390. DSS_PRM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
RM_RSTST_DSS RW 32 0x0000 0058 0x4830 6E58 C
PM_WKEN_DSS RW 32 0x0000 00A0 0x4830 6EA0 W
PM_WKDEP_DSS RW 32 0x0000 00C8 0x4830 6EC8 W
PM_PWSTCTRL_DSS RW 32 0x0000 00E0 0x4830 6EE0 W
PM_PWSTST_DSS R 32 0x0000 00E4 0x4830 6EE4 C
PM_PREPWSTST_DSS RW 32 0x0000 00E8 0x4830 6EE8 C
3.8.2.9.2 DSS_PRM Registers
Table 3-391. RM_RSTST_DSS
Address Offset 0x0000 0058
Physical Address 0x4830 6E58 Instance DSS_PRM
Description This register logs the different reset sources of the DSS domain. Each bit is set upon release of the
domain reset signal. Must be cleared by software.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
GLOBALCOLD_RST
DOMAINWKUP_RST
GLOBALWARM_RST
COREDOMAINWKUP_RST
602 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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