Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
Table 7-390. DSI_TIMING2
Address Offset 0x0000 005C
Physical Address 0x4804 FC5C Instance DSI_PROTOCOL_ENGINE
Description TIMING2 REGISTER This register controls the DSI Protocol Engine module timers. Any bit field can be
modified while
DSI_CTRL .IF_EN is set to 1. It is used to indicate the number of TxByteClkHS clock
cycles for the timers HS_TX_TIMER and LP_RX_TIMER
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HS_TX_TO_COUNTER LP_RX_TO_COUNTER
LP_RX_TO HS_TX_TO
LP_RX_TO_X4
HS_TX_TO_X8
LP_RX_TO_X16 HS_TX_TO_X16
Bits Field Name Description Type Reset
31 HS_TX_TO Enables the HS TX timer. RW 0x0
0x0: Turn-around counter is disabled.
0x1: Turn-around counter is enabled (required to receive TA interrupt
in case the turn-around procedure is not successful).
30 HS_TX_TO_X16 Multiplication factor for the number of TxByteClkHS functional clock RW 0x1
cycles defined in HS_TX_COUNTER bit field
0x0: The number of TxByteClkHS functional clock cycles defined in
HS_TX_TO_COUNTER is multiplied by 1x
0x1: The number of TxByteClkHS functional clock cycles defined in
HS_TX_TO_COUNTER is multiplied by 16x
29 HS_TX_TO_X8 Multiplication factor for the number of TxByteClkHS functional clock RW 0x1
cycles defined in HS_TX_COUNTER bit
0x0: The number of TxByteClkHS functional clock cycles defined in
HS_TX_TO_COUNTER is multiplied by 1x
0x1: The number of TxByteClkHS functional clock cycles defined in
HS_TX_TO_COUNTER is multiplied by 8x
28:16 HS_TX_TO_ HS_TX_TIMER counter. It indicates the number of TxByteClkHS RW 0x1FFF
COUNTER function clock cycles for the HS TX timer.
The value is from 0 to 8191.
15 LP_RX_TO Enables the LP RX timer. RW 0x0
0x0: Turn-around counter is disabled.
0x1: Turn-around counter is enabled (required to receive TA interrupt
in case the turn-around procedure is not successful).
14 LP_RX_TO_X16 Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1
defined in LP_RX_COUNTER bit field
0x0: The number of DSI_FCLK clock cycles defined in
LP_RX_TO_COUNTER is multiplied by 1x
0x1: The number of DSI_FCLK clock cycles defined in
LP_RX_TO_COUNTER is multiplied by 16x
13 LP_RX_TO_X4 Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1
defined in LP_RX_COUNTER bit
0x0: The number of DSI_FCLK clock cycles defined in
LP_RX_TO_COUNTER is multiplied by 1x
0x1: The number of DSI_FCLK clock cycles defined in
LP_RX_TO_COUNTER is multiplied by 4x
12:0 LP_RX_TO_ LP_RX_TIMER counter. It indicates the number of DSI_FCLK clock RW 0x1FFF
COUNTER cycles for the LP RX timer.
The value is from 0 to 8191.
1931 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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