icepick-006
ICEPick
Device JTAG IF
C64x+
TAP 1
ARM9
TAP 2
DAP
TAP 3
TAP
Reset,
clocks and
control
Secondary TAP IF
D2D
TAP 0
DSP
core
ARM9
core
DAP
Cortex-A8
ETM
ETB
DAP_PC
EPM
Public Version
www.ti.com
ICEPick Module
Table 27-1. JTAG Pins (continued)
PAD
Name
Width
Type
Reset
Description
(1)
Value
jtag_tck
Test Clock
1
I
HiZ
This is the test clock used to drive an IEEE 1149.1 TAP
state-machine and logic. Depending on the emulator
attached to the device, this is a free-running clock or a gated
clock, depending on RTCK monitoring.
jtag_rtck
Returned Test Clock
1
O
0
Synchronized TCK. Depending on the emulator attached to
the device, the JTAG signals are clocked from RTCK or
RTCK is monitored by the emulator to gate TCK.
jtag_tms
Test Mode Select
1
I
HiZ
Directs the next state of the IEEE 1149.1 TAP state-machine
jtag_tdi
Test Data Input
1
I
HiZ
Scans data input to the device
jtag_tdo
Test Data Output
1
O
HiZ
Scans data output of the device
jtag_emu0
Emulation 0
1
IO
HiZ
Channel 0 trigger – boot mode – HS-RTDX – trace port
jtag_emu1
Emulation 1
1
IO
HiZ
Channel 1 trigger – boot mode – HS-RTDX – trace port
For more information about ICEPick boot modes, see
The ICEPick module has a TAP state-machine consistent with the IEEE 1149.1 specification. For more
information about TAP states, see
27.2.3 ICEPick Integration
The ICEPick module is in the EMU power domain.
The ICEPick module use only JTAG clocks (jtag_tck and jtag_rtck). These clocks are external clocks and
are not managed by the device power, reset, and clock management (PRCM) module.
27.2.4 ICEPick Functional Description
27.2.4.1 ICEPick Block Diagram
is the block diagram of the ICEPick module with the four external (secondary) TAPs
connected to the ICEPick scan chain.
Figure 27-3. ICEPick Overview
3589
SWPU177N – December 2009 – Revised November 2010
Debug and Emulation
Copyright © 2009–2010, Texas Instruments Incorporated