Public Version
PRCM Functional Description
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3.5.3.3.2 CM
The CM clock generator generates interface clocks and peripheral functional clocks for most of the
modules. It also controls DPLL3, DPLL4, and the external peripheral clock output sys_clkout2 (see
The CM is in the CORE power domain, which can be powered off. When the CORE power domain is
powered off, the clocks are not available, and their off state is latched. The DPLL controls are also
latched. The RFF architecture ensures that the full CM setting is saved when the CORE power domain
goes to retention state, and is transparently restored when it reactivates.
DPLL3 receives SYS_CLK from the PRM module and generates CORE_CLK through the CM.
CORE_CLK is the source for the interface clocks (L3 and L4) and the functional clock . The L3 and L4
interface clocks supply the device interconnects and all module interface clocks. The L4 clock is divided
for USB (full-speed clock limitation at 50 MHz) and to supply the reset managers (PRM) in the WKUP
power domain. The clocks derived from CORE_CLK are fully balanced over the device.
The 96M_FCLK, 48M_FCLK, and 12M_FCLK clocks are functional unbalanced clocks for a number of
modules in the CORE and PER power domains.
The functional 96-MHz clock path can be bypassed with SYS_CLK to allow a peripheral such as I
2
C to
function while the DPLL4 is not powered on. The default configuration after initial power on is bypassed
with the system clock. Software must switch to the DPLL-generated clock after programming the system
settings.
The 96-MHz clock input from the PRM to the CM (CM_96M_FCLK) is internally gated by the CM.
is the functional overview of the CM.
298
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
