Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
Bits Field Name Description Type Reset
4 E4 Event #4 R 0
3 E3 Event #3 R 0
2 E2 Event #2 R 0
1 E1 Event #1 R 0
0 E0 Event #0 R 0
Table 5-273. Register Call Summary for Register TPCC_CER
IVA2.2 Subsystem Functional Description
• EDMA : [0] [1]
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [2]
Table 5-274. TPCC_CERH
Address Offset 0x101C
Physical address 0x01C0 101C Instance IVA2.2 TPCC
Description Chained Event Register (High Part):
If CERH.En bit is set (regardless of state of EERH.En), then the corresponding DMA channel is prioritized vs.
other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is
returned from one of the TPTCs through the completion interface, or is generated internally through Early
Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En
bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding
bit in the Event Missed Register is set. CERH.En cannot be set or cleared through software.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48 E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32
Bits Field Name Description Type Reset
31 E63 Event #63 R 0
30 E62 Event #62 R 0
29 E61 Event #61 R 0
28 E60 Event #60 R 0
27 E59 Event #59 R 0
26 E58 Event #58 R 0
25 E57 Event #57 R 0
24 E56 Event #56 R 0
23 E55 Event #55 R 0
22 E54 Event #54 R 0
21 E53 Event #53 R 0
20 E52 Event #52 R 0
19 E51 Event #51 R 0
18 E50 Event #50 R 0
17 E49 Event #49 R 0
16 E48 Event #48 R 0
15 E47 Event #47 R 0
14 E46 Event #46 R 0
13 E45 Event #45 R 0
12 E44 Event #44 R 0
11 E43 Event #43 R 0
10 E42 Event #42 R 0
899 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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