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IVA2.2 Subsystem Basic Programming Model
When servicing the interrupt exception, the CPU performs three steps:
1. Reads the IVA_IC.
register
2. Checks the error condition
3. Clears the error through the IVA_IC.
register
The dropped events that generate the INTERR event (EVT96) can be qualified by a mask register. CPU
interrupts that are to be ignored by the drop detection hardware can be masked in the IVA_IC.
register.
5.4.8.5
Interrupt Controller Basic Programming Model for Power Down of IVA2.2 Subsystem
When going to a low-power state not involving IVA2.2 logic power off, there are no special software
settings to perform. In particular, the noncombined interrupts can be used without any specific handling for
that power transition. To run the procedure for a correct transition to power-down state not involving
logic-off, the user must perform the following sequence:
1. Ensure that all wake-up events are correctly mapped to enabled DSP CPU interrupts, and are
unmasked in combined event registers (if combined events are used).
2. Clear associated bits in the
and
register to unmask wake-up
interrupts.
NOTE:
Software must not unmask in the WUGEN module an event that is not correctly mapped to
an enabled DSP CPU interrupt. If that event is triggered, the IVA2.2 subsystem exits the
power-down state but does not wake up.
The user must program the following procedure when transitioning to the (logic) power-off state (OFF
state for device):
1. Ensure that all wake-up events are correctly mapped to enabled DSP CPU interrupts, and are
unmasked in combined event registers (if combined events are used).
2. Clear correct bits in the
and
registers to unmask wake-up
interrupts.
3. Save necessary context (all except interrupt-related registers).
NOTE:
Steps 3 through 5 are automatic, but interruptible. If a wake-up interrupt occurs at this
stage, the transition to power down is canceled and the next transition restarts from the
beginning. Software tip: A software variable (semaphore) can be set in Step 3, modified in all
calls of the wake-up interrupt ISR routine, and checked before executing the IDLE instruction
in Step 5. For a complete description of the DSP CPU ISR register, see the C64x+
documentation (
4. Save the interrupt configuration in:
(a) IVA_IC.
register (where j = {1 to 3})
(b) IVA_IC.
register (optional, where i = {0 to 3})
(c) IVA_IC.
register (optional)
(d) DSP CPU IER register. See the C64x+ documentation for IER register description (
5. Execute the DSP IDLE instruction.
NOTE:
Software must not unmask in the WUGEN module an event that is not correctly mapped to
an enabled DSP CPU interrupt. If that event is triggered, the IVA2.2 subsystem exits the
power-down state but does not wake up.
5.4.8.6
Interrupt Controller Basic Programming Model for Power On of IVA2.2 Subsystem
Noncombined events can be lost after power on wakeup of the DSP megamodule module. To avoid this,
one solution is to replay the DSP CPU interrupt after restoring the interrupt selector and event combiner
context.
783
SWPU177N – December 2009 – Revised November 2010
IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
