Public Version
IVA2.2 Subsystem Basic Programming Model
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In the producer/consumer model, the cache-based producer typically ensures that the produced buffer
is visible to the consumer of that buffer by writing back the address range of that buffer and checking
for completion of the write-back sequence before sending a completion message to the consumer.
Example:
/* ---------------------------------------------------- */
/* nonCachedArea to be linked to non-cached SDRAM region*/
/* ---------------------------------------------------- */
#pragma DATA_SECTION(nonCachedDummyVar, ".nonCachedArea")
volatile int nonCachedDummyVar;
/* ---------------------------------------------------- */
/* outBuffer is produced buffer in SDRAM to be visible to the consumer */
/* ---------------------------------------------------- */
L2WBAR = &outBuffer[0];
L2WWC = sizeof(outBuffer) / sizeof(int);
/* ---------------------------------------------------- */
/* L2WWC ensures the sequence is completed by the cache controller but not completed in end
memory */
/* ---------------------------------------------------- */
while (L2WWC != 0)
;
/* ---------------------------------------------------- */
/*C64x+ is stalled until dummy memory read has completed which the hardware ensures happens after
write-back of outBuffer completed in SDRAM. */
/* ---------------------------------------------------- */
int dummyRead = nonCachedDummyVar;
/* ---------------------------------------------------- */
/* Then C64x SW (producer) can send message to consumer */
/* ---------------------------------------------------- */
•
sendCompletionMsgToConsumer();
NOTE:
To ensure completion, the nonCachedDummyVar must be in the same target as the
written-back buffer.
In the case of the C64x writing in the noncache area: To ensure the completion of the C64x write in
physical end memory, set the
[15] GEMTRUECOMPEN bit to 1 and also read back
after the last C64x write.
1. DSP write and DMA read
The user writes to some noncache region with DSP and then reads from the same area with DMA.
To ensure completion of the DSP write in physical end memory, set the SYSC.LICFG0[15]
GEMTRUECOMPEN bit to 1 and also read back after the last DSP write. The sequence is:
(a) Set the
[15] GEMTRUECOMPEN bit to 1.
(b) DSP writes data in external memory, noncache area.
(c) DSP reads data in external memory, noncache area: last write data for instance.
(d) DMA reads data from external memory.
2. DMA write and DSP read
The opposite of 1. To ensure the completion of DMA write in physical end memory, set the
DMATRUECOMPEN bit to 1 and PARAM [LCHi].OPT.TCCMODE to 0 (no early
completion). The sequence is:
(a) Set the
.DMATRUECOMPEN bit to 1.
(b) Set PARAM[LCHi].OPT.TCCMODE to 0.
(c) Set PARAM[LCHi].OPT.TCCMODE to 0.
(d) DSP waits for end of DMA transferred:
•
IPR/IPRH bit update (for polling-scheme)
•
Interrupt generation (for interrupt-scheme)
•
CER/CERH bit update (for chaining)
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IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
