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High-Speed USB Host Subsystem
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NOTE:
•
The PRCM CORE_120M_CLK output is cut at PRCM level assuming all the modules
that share it have been disabled in the corresponding register. Disabling the USBTLL
module is a necessary but not sufficient condition.
•
The PRCM CORE_L4_ICLK output is cut at PRCM level assuming all the modules that
share it have been disabled in the corresponding register. Disabling the USBTLL module
is a necessary but not sufficient condition.
•
The PRCM.CM_AUTOIDLE3_CORE[2] AUTO_USBTLL bit is used to link/unlink the
USBTLL module from CORE_L4_ICLK-related clock domain transitions.
•
For further details about source clocks gating and domain transitions, see
,
Power, Reset, and Clock Management.
At PRCM level, when all the conditions to shut off the USBTLL_FCLK or USBTLL_ICLK output clocks are
met (see
, Power, Reset, and Clock Management for details), the PRCM module automatically
launches a hardware handshake protocol to ensure the USBTLL module is ready to have its clocks
switched off. Namely, the PRCM asserts an IDLE request to the USBTLL module. Although this
handshake is completely hardware and out of any software control, the way in which the USBTLL module
acknowledges the PRCM IDLE request is configurable through the USBHOST.
[4:3]
SIDLEMODE bit field.
details SIDLEMODE settings and the related acknowledgment modes.
Table 22-42. USBTLL Module SIDLEMODE Settings
SIDLEMODE
Selected
Description
Value
Mode
0x0
Force-idle
The USBTLL module acknowledges unconditionally the IDLE request from the PRCM, regardless of
its internal operations. Because such a mode does not prevent any loss of data when the clock is
switched off, the mode must be used carefully.
0x1
No-idle
The USBTLL module never acknowledges any IDLE request from the PRCM. This mode is safe
from a module point of view as it ensures the clocks remain active; however, it is not efficient from a
power-saving perspective because it does not allow the PRCM output clock to be shut off and thus
the power domain to be set to a lower power state.
0x2
Smart-idle
The USBTLL module acknowledges the IDLE request basing its decision on its internal activity.
Namely, the acknowledge signal is asserted only when all pending transactions, IRQs or DMA
requests are treated. This is the best approach for an efficient system power management.
When configured in smart-idle mode, the USBTLL module also offers an additional granularity on
USBTLL_ICLK gating. The USBHOST.
[9:8] CLOCKACTIVITY bit is used to control
the USBTLL_ICLK clock internal gating while the module is idle.
details the CLOCKACTIVITY
settings.
Table 22-43. USBTLL Module CLOCKACTIVITY Settings
CLOCKACTIVIT USBTLL_ICLK Effect
Description
Y Value
0
OFF
USBTLL_ICLK is considered for generating the acknowledgment. This setting
also means USBTLL_ICLK is shut down upon PRCM IDLE request.
1
ON
USBTLL_ICLK is not shut down upon PRCM IDLE request. The USBTLL
module can potentially acknowledge the IDLE request without checking the
internal functionalities linked to its clock.
3268
High-Speed USB Host Subsystem and High-Speed USB OTG Controller
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated