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PRCM Basic Programming Model
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3.6.1.6
SRAM Precharge Time Control Register
3.6.1.6.1 PRM_SRAM_PCHARGE (Voltage SRAM Precharge Counter Register)
The voltage SRAM precharge counter register allows the setting of the precharge duration of the SRAM. It
has following bit field:
•
PCHARGE_TIME: Number of system clock cycles defined for the SRAM precharge duration
3.6.2 Clock Management Registers
3.6.2.1
System Clock Control Registers
3.6.2.1.1 PRM_CLKSRC_CTRL (Clock Source Control Register)
The clock source control register is dedicated to the clock source controls of the device. It contains the
following bit fields:
•
SYSCLKSEL: Indicates the oscillator mode (oscillator/bypass) and is automatically updated at power
up
•
AUTOEXTCLKMODE: Enables autogating for the system clock, depending on the device power state.
The clock can be configured to be automatically gated when all power domains are in either off or
retention state. When the gating condition is satisfied, the internal oscillator is turned off, if it is used.
Otherwise, sys_clkreq is asserted to notify the external clock source to turn off.
NOTE:
Power consumption is reduced with the SYS_CLK off; however, wake-up latency is
increased because of oscillator stabilization time after the clock is turned on again.
•
SYSCLKDIV: Input divider (1, 2) of the system clock
3.6.2.1.2 PRM_CLKSETUP (Source-Clock Setup Register)
The source-clock setup register allows the setting of the setup time of the oscillator system clock, based
on the number of 32-kHz clock cycles. This duration corresponds to the time required by the oscillator to
stabilize before propagating the system clock.
Because the reset lasts long enough for oscillator stabilization, this register is not used at power-on reset
of the device. This is ensured either by the external reset source (power IC) or by the reset extension in
the PRCM module (RSTTIME0 timer). The
register is cleared on cold reset only.
NOTE:
The clock setup time is implemented using the oscillator mode or the external clock mode
(bypass mode). (The mode of the oscillator is selected by the SYSCLKSEL bits in the
register).
3.6.2.1.3 PRM_CLKSEL (Source-Clock Selection Register)
The PRCM.PRM_CKSEL[2:0] SYS_CLKIN_SEL bit field is used to select the input frequency of the
system clock (12, 13, 16.8, 19.2, 26 or 38.4 MHz).
3.6.2.2
External Clock Output Control Registers
3.6.2.2.1 PRM_CLKOUT_CTRL (Clock Out Control Register)
The PRM clock out control register provides control to enable and disable the gating of the sys_clkout1
output clock.
402
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
