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Display Subsystem Functional Description
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One or multiple VCs can be synchronized using the same TE trigger. The DSS.
[30] TE_EN
bit should be set to indicate that the hardware should use the following TE trigger to start the transfer of
the data from the related VC. This bit is reset when all the data have been sent to the peripheral. The
DSS.
[31] TE_START bit should be used when the automatic mode enabled by setting the
[30] TE_EN bit is not used. It allows users to start the transfer manually based on
application events or based on the TE trigger interrupt (TE_TRIGGER_IRQ).
The number of bytes to be transferred is defined by using the DSS.
[15:0] TE_SIZE bit field.
The TE_SIZE bit field is decremented for each payload byte (it does not include Check-sum) sent on the
DSI link. The register content should not be modified by software during a transfer. The
DSS.
[15:0] TE_SIZE bit field should be set first to indicate that the following accesses to
register should be used for TE transfer.
The data can be provided from two sources (selection by setting the DSS.
[1] SOURCE
bit):
•
L4 interconnect port using DMA request: The DMA request DSI_DMA_REQi (i=0 to 3) to should be
asserted only when TE trigger is received or when the DSS.
[31] TE_START bit is set by
user and should not be asserted anymore when all the bytes defined in DSS.
[15:0]
TE_SIZE bit field have been sent on the DSI link. The VC is associated with a DMA request (from
DSI_DMA_REQ0 to DSI_DMA_REQ3) by programming the number in the
DSS.
[23:21] DMA_TX_REQ_NB bit field. The
DSS.
register is used to provide the number of bytes defined by
the DSS.
[15:0] TE_SIZE bit field (the check-sum value is not provided in the
DSS.
register). The size of the header is not taken into account
in the number of bytes to transfer. The DSS.
register is not
used.
•
Video port: The DMA request is not asserted. The data are captured in the line buffer using the STALL
mechanism. In case there is no line buffer instantiated (that is, DSS.
[13:12] LINE_BUFFER
bit field set to 0), it is not possible to use the video port to provide data. The line buffer should be filled
up according to the word count defined in the DSS.
register
header. The value should be written before the TE trigger event is received or before the
DSS.
[31] TE_START bit is set to 1 by software. In case the total number of bytes defined
by the DSS.
[15:0] TE_SIZE bit field is not a multiple of the word count defined in the
DSS.
register, all the packets have the same size defined by the
WC of the header except the last transfer. The size of the last transfer is defined by the remaining
bytes to send. Since the DSS.
[15:0] TE_SIZE bit field is modified after each packet
transfer, the size of the last packet is equal to the value of DSS.
[15:0] TE_SIZE bit field
just before the last transfer (the header and the payload check-sum sizes are not included in
DSS.
[15:0] TE_SIZE bit field).
When the transfer is completed, the value of the DSS.
[15:0] TE_SIZE bit field is equal to 0.
The software must ensure that the pending data in the TX FIFO for the corresponding VC using TE are
related to TE transfer. Any data in the TX FIFO that should be sent before reception of TE trigger should
be sent before TE. This is done by not enabling TE trigger until all data for the corresponding VC have
been sent to the peripheral. The software can check that the space allocated for the VC in the TX FIFO is
empty by reading the DSS.
[5] TX_FIFO_NOT_EMPTY status bit.
7.4.3.9.3 Acknowledge
The corresponding Acknowledge interrupt (ACK_TRIGGER_IRQ ) is generated upon reception of the
acknowledge trigger. The value of the expected acknowledge trigger pattern can be configured through
the
[15:8] REG_RXTRIGGERESC1 bit field. To enable the acknowledge interrupt,
set the DSS.
[17] ACK_TRIGGER_IRQ_EN bit to 1. When the interrupt is generated, the
[17] ACK_TRIGGER_IRQ status bit is set to 1.
1682
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
