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L3 Interconnect
Table 9-66. RT Register Summary
Register Name
Type
Register
Address Offset
Physical Address
Width (Bits)
R
64
0x000
0x6800 0000
R
64
0x010
0x6800 0010
R
64
0x070
0x6800 0070
RW
64
0x078
0x6800 0078
9.2.5.3.1 Register Target (RT) Registers Description
Table 9-67. L3_RT_COMPONENT
Address Offset
0x000
Physical Address
0x6800 0000
Instance
RT
Description
This register identifies the component to which this register block belongs.
Type
R
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CODE
REV
Bits
Field Name
Description
Type
Reset
63:32
Reserved
Reserved
R
0x00000000
31:16
CODE
Component Code
R
See
(1)
.
15:0
REV
Revision of the component
R
See
(1)
.
(1)
TI Internal Data
Table 9-68. Register Call Summary for Register L3_RT_COMPONENT
L3 Interconnect
•
Table 9-69. L3_RT_NETWORK
Address Offset
0x010
Physical Address
0x6800 0010
Instance
RT
Description
This register identifies the interconnect and is present only in the register target.
Type
R
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
Bits
Field Name
Description
Type
Reset
63:32
ID
Unique Interconnect ID
R
0x00000000
31:0
Reserved
Reserved
R
0x00000000
2041
SWPU177N – December 2009 – Revised November 2010
Interconnect
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